What is LPC43xx SPFI Prefetch Cache and CMD RX/TX FIFO Sizes

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by sgstreet on Thu May 28 09:26:04 MST 2015
Hi All,

I attempting to run a LPC4370 Design with a WIN25Q80BV SPI Flash at the fastest possible speed (i.e. BASE_SPIFI_CLK at 102MHz).  The WIN25Q80BV supports a "Octal Word Read Quad I/O (E3h) With Continuous Read Mode" (see http://partner.winbond.com/NR/rdonlyres/4D2BF674-7427-4FC8-AEF0-1A534DF74F16/0/W25Q80BV.pdf Section 6.2.17) which I'm trying to use.  The requirement is that address bits A0-A3 must be zero which forces a 16 byte read alignment. 

I have not been able find any information in LPC43xx User's Manual describing how the Memory Mode generates read addresses for the SPI Flash.  I have the following questions concerning the SPIFI peripheral:

- What is the size of SPIFI prefetch cache?
- What is size and address alignment of SPIFI Memory Mode read commands?
- What is the difference in Memory Mode behaviour when LPC_SPFI MCDM[FRAMEFORM] is 0x0 verses 0x6.  Values 0x0 is designated as reserved but used by the SPFI ROM Bootloader for "Continuous Read Mode" while 0x6 appears to be the correct value but does not work with "Continuous Read Mode".

- In Command Mode, what is the underlying TX/RX FIFO size?
- In Command Mode, how is TX/RX FIFO empy/full handled?  Bus stall, overrun, underrun?