Yet another +5V tolerant IOs question

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by sasa.bremec on Mon Dec 02 04:41:05 MST 2013
Hi to all.

Reading footnotes in the LPC43xx data sheet I found the lines below:

+5 V tolerant pad providing digital I/O functions (with TTL levels and hysteresis) and analog input or output (5 V tolerant if VDDIO present; if VDDIO not present, do not exceed 3.6 V).

So if I want to have 5V outpust do I connect 3V3 or 5V on the VDDIO.
In the datasheet pg. 89 Limiting values there is a line  Vi  mar = 5.5V when VDD(IO)[u]>[/u]2.2V   5V tolerant digital I/O pins.

Unfortunately the same statement is in the UM.

Thanks, Sash