Timer/RIT: write clear interrupt flag to 1, read as 0, when?

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by petekol on Sun Nov 01 07:04:59 MST 2015

i have some understanding problem of clearing an interrupt flag of RIT:
i expect that harware clears the flag to 0 and a can read it as 0 after i write 1 to it. In practice i do not read 0 event if doing it in a loop for ever (in ISR).

Does it means that it is acctually cleared internally by writing 1 an i can't read it as 0 (only after exit from ISR?) but if i move compare value then it fire interrupt next time.

So tha question is when i should expect to read the flag as 0? Before this time and after i write 1 to it can i trigger one more compare fire (flag goes to 1)?