lpc4357 IPC Blinky example

[lpcware]

Content originally posted in LPCWare by pgeloso on Tue Mar 31 02:31:46 MST 2015
Hi,
I'm using LPC4357 ea Board with LPCXpresso v7 and I'm running the dual core example  dc_sa_blinky/dc_sa_blinky_m0.
Reading the code of the m0 I see something that I don't understand about this IPC communication example.

The dimension of the SRAM assigned to m0 in MCU Settings is 32KB (while I expect it should be 40KB):
SRAM start 0x1008.0000, size 0x8000.
In the code the m0 will access the SRAM starting  from the absolute address
#define SHARED_MEM_M0          0x10089F80
that is beyond the SRAM limit defined for the m0.

Could you help me to understand this point?

Thanks
Pietro

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Wed Apr 01 18:40:18 MST 2015
Hi Pietro,
Both cores can access entire SRAM space.
The defines for SHARED memory is used for IPC communication.
The MCU setting defines the memory regions only. It does not define which core uses which memory.
regards,