lpcware

SDRAM controller

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by PhilYoung on Thu Apr 05 10:49:12 MST 2012
Trying again, so apologires if this gets duplicated.
I'm having difficulty getting SDRAM to work with the M4 running at 200 MHz.
I modified the SDRAM example to get a 128 Mb 32 bit 4 bank SDRAM working reliably at 100 MHz, and extended the SDRAM tests to be much more exhaustive and over a larger area.
I also tested the SDRAM in both ROW_BANK_COLUMN and BANK_ROW_COLUMN configurations, both work perfectly with the CPU at 100 MHz and not at 200 MHz.

then Added the following code to set the EMC to operate at 100 MHz withh the CPU at 200 MHz using EMC_CLK_DIV.

   LPC_CCU1->CLK_M4_EMCDIV_CFG = 0x21; // enabled / divide by 2 for 100Mhz
   LPC_CREG->CREG6 = LPC_CREG->CREG6  | 0x10000; // set EMC_CLK_SEL

( the obvious thinh would be timing parameters, but I use 10ns for the clock period in both cases rather than the system reported CPU clock speed used in the example).

I find very strange behaviour, at 100MHZ the SDRAM is 100% reliable, but using exactly the same setup, only changing the CPU clock and using EMC_CLK_DIV the SDRAM starts to show a failure of about 0.1% write errors.

The write errors take 2 forms.
Sometimes a number of 4 word blocks simply don't get updated ( each location has a unique value and the value does not appear elswehere ).
At other times I get data duplication, always if I expect Y at location (X) and Z at location (X + 16) ( 4 words later ) I actually find Z at both locations.

This is very strange behaviour, I've seen similar behaviour years ago with SRAM, but the failure mechanism that caused duplicated writes there should be impossible in SDRAM.

Has anybody else tried using the SDRAM controller at half the CPU speed with the CPU at 200 MHz?.

has anybody got any suggestions ( I spent 2 days trawling through the SDRAM and LPC4350 manuals and cannot see anything wrong ).

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