Cortex-M0 and SPIFI

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by peufeu on Fri Mar 08 00:36:28 MST 2013
Hello !

I'm making an application that will communicate via ethernet, using a stream of UDP packets, and also USB.

I'd like to have the Cortex-M0 handle the communication tasks, and present a simple "pipe" interface to the M4, which will apply some DSP on the data. The docs about IPC between the cores seem to indicate this should not be too complicated. Basically the M0 will rx and tx UDP packets (handling retransmissions if needed), generate and parse IP/UDP headers, handle ARP, USB, etc. The M0 will be a sort of smart network/USB interface. So the M4 will be entirely available for DSP, it doesn't need to know the details of where the data comes from or where it goes.

The cpu will be LPC4330 with a spifi flash, I'm using LPCXpresso, and right now LPC4330-Xplorer.

I'd like to keep RAM for buffers, which means moving some of the code to SPIFI flash, especially code that isn't speed-critical, like initializations, ARP, USB descriptors, etc.

Question is : how can I tweak the project and link settings to put some of the M0 code in SPIFI flash ? The Dual Core examples put it all in RAM, which I'd like to avoid, ideally. I haven't found the info about how the address mappings work ; ok, the M0's zero memory address is shifted so its vectors are put where we want it, but it also accesses shared memory, so those addresses must not be shifted, right ?