SGPIO: External clock qualifier signal use

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by ZZZMQP on Fri Feb 12 07:08:22 MST 2016
I started evaluating the LPC4337 on the LPCXpresso4337 V3 board for a new project.

I set up one SGPIO slice for now (D) with 4 bit wide input, external clock (SGPIO8) and external clock qualifier (SGPIO9). I get the exchange interrupt whenever REG and REG_SS swap. That seems to be working fine.

However, the data I get in is part of large packets (several hundred bytes long) and the clock qualifier signal is basically a 'data valid' signal that tells me when a new packet begins (rising edge) and when it ends (falling edge). In order to reassemble the incoming stream into the large packets, I need to evaluate the 'data valid' signal to know when to start a new buffer (= new packet) and when to switch to the next buffer (packet).

I think it's not possible to also trigger a 'pin' interrupt on the SGPIO9 pin as it is configured as a SGPIO (not GPIO) pin.

I guess I could feed the 'data valid' signal to a regular GPIO pin (in parallel to SGPIO9) and trigger PIN interrupts on edges, but that's probably too slow. The external SGPIO clock is 25 MHz and processing the GPIO interrupt will take too long.

I'm looking for some advise here...  seems to be a common us case. What is the proper way to handle the re-assembly of the packet for the required performance?

Forgot to mention that this runs on the M0 core...   thanks.