LPC43xx External Static Memory - Read/Write buffering

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by lochkartenman on Wed Oct 01 10:52:05 MST 2014
We would like to tightly-couple a FPGA with a µC by means of the external static memory memory controller, thereby effectively mapping the FPGA registers into main memory of the µC with maximum bandwidth. At the moment we plan with 8-bit address & data and async. static NOR like interfacing.

For this setup it is necessary that each and every read/write is actually transmitted to the FPGA (memory) device and no buffering takes place. Since I am still new to the the LPC43xx family I wonder whether disabling buffers in the Static Memory Configuration registers is sufficient.