lpcware

NVIC_DisableIrq latency? Inline but needs delay.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by h11angel on Thu Mar 28 05:26:41 MST 2013
Hi guys.

Long story short, I was trying to enable an interrupt for the SGPIO when I observed the following:

If a certain number of neutral cycles are not inserted between
NVIC_DisableIRQ(Periph_IRQn)
and
LPC_Periph->SET_EN_PeriphInt = (PeriphIntMask);
the interrupt will not be enabled.

In order to enable my interrupt for the SGPIO I was forced to use:

NVIC_DisableIRQ(SGPIO_IINT_IRQn);
[color=red]for (int i=0;i<5;i++);[/color]
LPC_SGPIO->SET_EN_0 = (1<<DATA_CFG0.sliceId);


I've used a human powered binary search to find the value for i<5;
This, when disassembled, translates into 1 cycle for loading i, 5 compares, 5 branch-lesser-than's and 1 last compare. In total of 12 cycles. With 10 cycles it still doesn't work.

My LPC4330 is running at 204MHz and I'm debugging using the IAR-Jlink toolchain. Now, I don't remember reading about this delay in neither the CM3 or the CM4 user manuals.

Does anybody know what this is all about? If not, watch out for this if you can't enable your interrupts.

Regards!


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