NVIC_DisableIrq latency? Inline but needs delay.

[lpcware]

Content originally posted in LPCWare by h11angel on Thu Mar 28 05:26:41 MST 2013
Hi guys.

Long story short, I was trying to enable an interrupt for the SGPIO when I observed the following:

If a certain number of neutral cycles are not inserted between
NVIC_DisableIRQ(Periph_IRQn)
and
LPC_Periph->SET_EN_PeriphInt = (PeriphIntMask);
the interrupt will not be enabled.

In order to enable my interrupt for the SGPIO I was forced to use:

NVIC_DisableIRQ(SGPIO_IINT_IRQn);
[color=red]for (int i=0;i<5;i++);[/color]
LPC_SGPIO->SET_EN_0 = (1<<DATA_CFG0.sliceId);

I've used a human powered binary search to find the value for i<5;
This, when disassembled, translates into 1 cycle for loading i, 5 compares, 5 branch-lesser-than's and 1 last compare. In total of 12 cycles. With 10 cycles it still doesn't work.

My LPC4330 is running at 204MHz and I'm debugging using the IAR-Jlink toolchain. Now, I don't remember reading about this delay in neither the CM3 or the CM4 user manuals.

Does anybody know what this is all about? If not, watch out for this if you can't enable your interrupts.

Regards!

[lpcware]

Content originally posted in LPCWare by pierre on Mon Apr 08 00:16:44 MST 2013

You need to set the frequency and enable the base and branch clocks for SGPIO, but you've probably done this already..

Datasheet mentions the latency for reads and writes to SGPIO registers, which is quite large, and includes 2-4 SGPIO clocks.

Thus, if your SGPIO clock is slow (in my case it was 25 MHz) relative to main cpu clock, SGPIO register writes will be extremely slow, making the SGPIO IRQ a major cpu hog. Solution is increasing SGPIO frequency and playing with the dividers.

Anyway, I'd like to see the rest of your code, especially the part with the NVIC_EnableIRQ. Here you disable the IRQ and complain it doesn't work, but I guess you must call NVIC_EnableIRQ somewhere... perhaps the delay plays with the interaction of NVIC_EnableIRQ and the enabling of interrupts in the SGPIO registers ? I did not have this problem. Strange.

[lpcware]

Content originally posted in LPCWare by suckfish on Mon Apr 01 19:20:08 MST 2013
How is the clocking set up for SGPIO in the CGU & CCU?

My reading of the user manual is that SGPIO is clocked by the 12MHz IRC clock by default & that could explain a dozen cycles or so of latency in interrupt set-up.

If you haven't already, you could try changing the BASE_PERIPH_CLOCK to the same clock as the CPU and see if that makes any difference.

Anyway, thanks for the heads up on this, that's the sort of unexpected little issue that can cause days of head scratching!