lpcware

LPC4370 SGPIO one-shot madness.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by David Lee on Fri Jun 06 13:53:29 MST 2014
I've configured a few slices to generate a custom serial interface. It has typical stuff like CHIP_SELECT, SERIAL_CLOCK, DATA, etc.
It runs in one-shot mode, sending a data payload of 24 bits. The single transmission is controlled according to the documentation
in the user manual (UM10503.PDF) Sec. 19.6.17.

It worked solid as a rock during testing with a simple data pattern like 0x00AA00AA.

So I decided to test it by sending random data payloads and I noticed on my scope that infrequently, the slices fail
to stop after 1 "cycle". That is to say, I see two transmission sequences back to back. Yuck! The failure is data dependent!!!???

I am starting the slices like this:


Quote:
// Start SGPIO operation by enabling slice clocks.
LPC_SGPIO->CTRL_ENABLED = m_controlMask;
//We only want 1 countdown cycle (1 transmission) so this will stop when POS reaches zero.
LPC_SGPIO->CTRL_DISABLED = m_controlMask;



This is the recommended process from Sec. 19.6.17.

In desperation, I tried reversing the order, in contradiction to Sec. 19.6.17:

Quote:
//Try setting CTRL_DISABLE BEFORE CTRL_ENABLE. This contradicts 19.6.17 in user manual!
//We only want 1 countdown cycle (1 transmission) so this will stop when POS reaches zero.
LPC_SGPIO->CTRL_DISABLED = m_controlMask;
// Start SGPIO operation by enabling slice clocks.
LPC_SGPIO->CTRL_ENABLED = m_controlMask;



The result is rock solid transmission with NO observable anomalous transmissions.

I would be grateful for help with this issue. I really, really do not like getting code to work by swapping the order
of commands willy nilly. Especially when it directly contradicts the documentation.

A little help?

Cheers,
David

Note. There's a typo in Sec 19.6.17:

Quote:
this register should always be cleared. If
only on POSi countdown is needed



should read:

Quote:
this register should always be cleared. If
only one POSi countdown is needed

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