lpcware

mixing up data lines at SDRAM

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by khfreiberg on Wed Mar 19 15:17:25 MST 2014
Hi,
I have a question to layout optimization.
At normal SRAM it is no problem to mixup the data lines, since it comes out as it got in.
I have two 16bit SDRAMS to form a 32bit bus (using CLK1/CLK3). I have seen AN10935, AN10778 and AN11508.
The SDRAM layout is quite critical concerning length matching so I would like to optimize by swapping data lines. I did not found an exact description how the EMC deals with DMQOUT lines. I assume in 32bit configuration DMQOUT0...3 are driven in parallel. Looks like there is nothing that prevent me from doing this. Do I miss something ? 

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