SSP: Discrepancies between User Manual and Datasheet

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by mysepp on Thu May 07 21:50:58 MST 2015

I want to use SSP (Master and Slave) on LPC43xx. When comparing the user manual UM10503 (Rev. 1.9 - 18 Feb. 2015)
to the latest Datasheet LPC435X_3X_2X_1X.pdf (Rev. 5 - 28. April 2015) I found some discrepancies.

1) "Clocks"

From User Manual (Chapter 42, Page 1165):
Clock to SSP0 register interface BASE_M4_CLK CLK_M4_SSP0 [color=#f30]up to 204 MHz[/color]
SSP0 peripheral clock (PCLK) BASE_SSP0_CLK CLK_APB0_SSP0 [color=#f30]up to 204 MHz[/color]
Clock to SSP1 register interface BASE_M4_CLK CLK_M4_SSP1 [color=#f30]up to 204 MHz[/color]
SSP1 peripheral clock (PCLK) BASE_SSP1_CLK CLK_APB2_SSP1 [color=#f30]up to 204 MHz[/color]

so I assume there so no limitation for Master nor Slave.

But in Datasheet (Chapter 11.11, Page 17) there is a limitation for SSP slave:
Tcy(PCLK) PCLK cycle time 10 ns
Tcy(clk) clock cycle time [2] 120 - - ns

which seems to be a limitation to [color=#f30]100 MHz and 8,33 MBit[/color].

What is correct?

Just for my info:
We used 204 MHz and speeds higher than 10 MBit/s on a LPC4357. What is the problem that CLK and speed is limited?
Are there errors which don't occur when using only 100 MHz and lower than 8,33 MBit/s?

2) Again on this 100 MHz, the 204 MHz, when dividing by 2 comes to 102 MHz. But 102 MHz is still out of spec, according to datasheet.
Can you confirm or reject that 102 MHz is still in a valid range?

3) Table 26 list Tcy(clk) as first entry (outside master/slave section), so this is for all?
Why is there a "typical", shall it not be "min"?

4) What about the other numbers in datasheet? Are they correct? Or are there known wrong numbers?

Thanks for clarification!

Best regards,