lpcware

LPC4357 Core M0 features

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by DT1 on Tue Apr 01 13:40:27 MST 2014
Hi,

I'm not sure I understand perfectly what is shared between the M4 and M0 and what is specific. According to the user manual, almost everything is shared between the 2 cores by the matrix, but I still have some interrogations...

[list]
  [*]Is the FPU available to the core M0 (through the LPC4357 overall core) of it's only available to the core M4?
  [*]If I use an external SDRAM in both cores through EMC (not at the same time), must I do something special in the M0? I'm asking because I'm under the impression that accessing the SDRAM from the M0 is a little slower than from the M4. Must I enable a specific clock or configure a specific clock related to the M0?
  [*]Is the M0 clock automatically enabled or must I do something special to ensure it is running at the same frequency than my M4 (156MHz)?
[/list]

My current CGU init is like this:


uint32_tCGU_Init(void)
{
uint32_t idx = 0;

CGU_SetXTALOSC(12000000);
CGU_EnableEntity(CGU_CLKSRC_XTAL_OSC, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_BASE_M4);

// Wait 100us
for (idx = 0; idx < 10000; ++idx);

CGU_EntityConnect(CGU_CLKSRC_XTAL_OSC, CGU_CLKSRC_PLL1);
//CGU_SetPLL1(6);// 72 MHz
//CGU_SetPLL1(10);// 120 MHz
CGU_SetPLL1(13);// 156 MHz
//CGU_SetPLL1(16);// 192 MHz

CGU_EnableEntity(CGU_CLKSRC_PLL1, ENABLE);
CGU_EntityConnect(CGU_CLKSRC_PLL1, CGU_BASE_M4);

CGU_UpdateClock();
return 0;
}


Followed later on by the SDRAM init function:


LPC_CCU1->CLK_M4_EMC_CFG = (1 << 2) | (1 << 1) | 1;
  while (!(LPC_CCU1->CLK_M4_EMC_STAT & 1));
...
  div = 0;
  if (SystemCoreClock > 120000000UL) {
    /* Use EMC clock divider and EMC clock output delay */
    div = 1;
    /* Following code must be executed in RAM to ensure stable operation      */
    /* LPC_CCU1->CLK_M4_EMCDIV_CFG = (1 << 5) | (1 << 2) | (1 << 1) | 1;      */
    /* LPC_CREG->CREG6 |= (1 << 16);       // EMC_CLK_DIV divided by 2        */
    /* while (!(LPC_CCU1->CLK_M4_EMCDIV_STAT & 1));                           */

    /* This code configures EMC clock divider and is executed in RAM          */
    for (n = 0; n < emcdivby2_szw; n++) {
      emcdivby2_buf[n] =  *((uint32_t *)emcdivby2_ram + n);
      *((uint32_t *)emcdivby2_ram + n) = *((uint32_t *)emcdivby2_opc + n);
    }
    __ISB();
    ((emcdivby2 )(emcdivby2_ram+1))(&LPC_CREG->CREG6, &LPC_CCU1->CLK_M4_EMCDIV_CFG, (1 << 5) | (1 << 2) | (1 << 1) | 1);
    for (n = 0; n < emcdivby2_szw; n++) {
      *((uint32_t *)emcdivby2_ram + n) = emcdivby2_buf[n];
    }
  }


Thanks!

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