lpcware

LPC4337 SGPIO external clock input

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by eva_lpc on Tue Aug 19 07:31:46 MST 2014
I'm trying to make a simple SGPIO example in which slice A is shifting out data, but with the shift clock provided on an external pin, SGPIO9.

        // Disable all counters during configuration
LPC_SGPIO->CTRL_ENABLED = 0;

//set pin to SGPIO mode
Chip_SCU_PinMuxSet(0,0, SCU_MODE_FUNC3);   //SGPIO0, the output pin
Chip_SCU_PinMuxSet(1,2, SCU_MODE_FUNC3);   //SGPIO9, the clk input pin

        //Connect SGPIO clock to Main_PLL
        Chip_Clock_SetBaseClock(CLK_BASE_PERIPH, CLKIN_MAINPLL, true, false);
      
        // SGPIO pin 0 outputs slice A bit 0.
LPC_SGPIO->OUT_MUX_CFG[0] =
(0L <<  4) |    // P_OE_CFG
        (0L <<  0);     // P_OUT_CFG = 0, dout_doutm1 (1-bit mode)

        // Configure Slice A
LPC_SGPIO->SGPIO_MUX_CFG[0] =
(0L << 12) |    // CONCAT_ORDER = 0 (self-loop)
(1L << 11) |    // CONCAT_ENABLE = 1 (concatenate data)
(0L <<  9) |    // QUALIFIER_SLICE_MODE = X
(0L <<  7) |    // QUALIFIER_PIN_MODE = X
(0L <<  5) |    // QUALIFIER_MODE = 0 (enable)
(0L <<  3) |    // CLK_SOURCE_SLICE_MODE = X
(1L <<  1) |    // CLK_SOURCE_PIN_MODE (1) = SGPIO9
(1L <<  0);     // EXT_CLK_ENABLE = 1, external clock

LPC_SGPIO->SLICE_MUX_CFG[0] =
(0L <<  8) |    // INV_QUALIFIER = 0 (use normal qualifier)
(0L <<  6) |    // PARALLEL_MODE = 0 (shift 1 bit per clock)
(0L <<  4) |    // DATA_CAPTURE_MODE = 0 (detect rising edge)
(0L <<  3) |    // INV_OUT_CLK = 0 (normal clock)
(1L <<  2) |    // CLKGEN_MODE = 1 (use external clock)
(0L <<  1) |    // CLK_CAPTURE_MODE = 0 (use rising clock edge)
(0L <<  0);     // MATCH_MODE = 0 (do not match data)

        LPC_SGPIO->PRESET[0] = 0;
LPC_SGPIO->COUNT[0] = 0;
LPC_SGPIO->POS[0] = (0x1FL << 8) | (0x1FL << 0);
LPC_SGPIO->REG[0] = 0xAAAAAAAA;     // Primary output data register
LPC_SGPIO->REG_SS[0] = 0xAAAAAAAA;  // Shadow output data register

        LPC_SGPIO->CTRL_ENABLED = (1L <<  0);     // Slice A enabled


When CLKGEN_MODE bit is disabled, Slice A outputs a 50% duty cycle signal at SGPIO_CLK rate. However, when CLKGEN_MODE bit is set, there is no output, maybe because the external clock input is not configured correctly. Am I forgetting something?

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