I'm designing a board using the LPC4357FET256 and want to use the maximum amount of SDRAM available per chip select (only the first CS will be populated initially but others may be later)
By far the cheapest solution is to use two RAM chips each in 64Mx16 configuration on each bus or a single chip in 64Mx32 configuration, however looking at the manual (page 484) it only gives an EMC address configuration option for using 4 chips in 64Mx8 configuration. This seems to be the only method that will allow me to use the maximum 2Gb per CS but not only works out more expensive than the other options but also takes up a lot more board space. Is it possible to set the address configuration to 64Mx8 and still only use two 64Mx16 chips or a single 64Mx32 chip?
I'm not sure how this would impact the number of rows and columns required but I would have thought it would be the same since the address space is identical, I'm simply splitting the 32 bit word into 1 or 2 instead of 4.