SDRAM configuration

lpcware · ‎06-15-2016

Content originally posted in LPCWare by tom-gds on Thu May 16 03:02:17 MST 2013

I'm designing a board using the LPC4357FET256 and want to use the maximum amount of SDRAM available per chip select (only the first CS will be populated initially but others may be later)

By far the cheapest solution is to use two RAM chips each in 64Mx16 configuration on each bus or a single chip in 64Mx32 configuration, however looking at the manual (page 484) it only gives an EMC address configuration option for using 4 chips in 64Mx8 configuration. This seems to be the only method that will allow me to use the maximum 2Gb per CS but not only works out more expensive than the other options but also takes up a lot more board space. Is it possible to set the address configuration to 64Mx8 and still only use two 64Mx16 chips or a single 64Mx32 chip?

I'm not sure how this would impact the number of rows and columns required but I would have thought it would be the same since the address space is identical, I'm simply splitting the 32 bit word into 1 or 2 instead of 4.

Thanks,

Tom

lpcware · ‎06-15-2016

Content originally posted in LPCWare by bavarian on Fri May 24 10:09:45 MST 2013

Hello Tom,

you can achieve the maximum SDRAM size for example with this configuration:

- use two 16-bit memories in parallel, one gets connected to DQMOUT[1:0], the other one to DQMOUT[3:2], both on DYCS[0]

- we achieved this e.g. with MT48LC16M16 (256Mbit(16Mb x 4 x 4 bank)

There is an app note here: http://www.lpcware.com/content/nxpfile/an10935-using-sdrddr-sdram-memories-lpc32xx

... which gives some good information about SDRAM. Its for another processor, but the SDRAM part is true for the LPC4300 as well.

A possible init sequence is shown below:

#if (USE_EXT_DYN_MEM_CS0)
 LPC_SCU->EMCDELAYCLK = 0x00005555;
 /* Set Address mapping for MT48LC16M16 cascaded as 32-bit memory: */
 /* 256Mbit(16Mb x 4 x 4 banks), row len = 13, column len = 10 */
 /* bit[14] = 1 bit]11:9] = 100 bit[8:7] = 01 */
 LPC_EMC->DYNAMICCONFIG0 = (1 << 14) | /* AM[14] = 1 */
 (0 << 12) | /* AM[12] = 0 */
 (4 << 9) | /* AM[11:9] = 4 */
 (1 << 7) ; /* AM[8:7] = 1 */
 LPC_EMC->DYNAMICRASCAS0 = 0x00000303; /* Latency: RAS 3, CAS 3 CCLK cyc.*/
 LPC_EMC->DYNAMICREADCONFIG = 0x00000001; /* Command delayed by 1/2 CCLK *
 LPC_EMC->DYNAMICRP = 1; 
 LPC_EMC->DYNAMICRAS = 3;
 LPC_EMC->DYNAMICSREX = 6; 
 LPC_EMC->DYNAMICAPR = 0; 
 LPC_EMC->DYNAMICDAL = 5; 
 LPC_EMC->DYNAMICWR = 1;
 LPC_EMC->DYNAMICRC = 5; 
 LPC_EMC->DYNAMICRFC = 5; 
 LPC_EMC->DYNAMICXSR = 6; 
 LPC_EMC->DYNAMICRRD = 0;
 LPC_EMC->DYNAMICMRD = 0; 
 WaitUs (10);
 LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
 WaitUs (10);
 LPC_EMC->DYNAMICCONTROL = 0x00000103; /* Issue PALL command */
 WaitUs (1);
 LPC_EMC->DYNAMICCONTROL = 0x00000183; /* Issue NOP command */
 WaitUs (1);
 LPC_EMC->DYNAMICREFRESH = 2; //EMC_NANOSEC( 200, SystemCoreClock, div) / 16 + 1;
 WaitUs (10);
 LPC_EMC->DYNAMICREFRESH = 110; //EMC_NANOSEC(15625, SystemCoreClock, div) / 16 + 1;
 WaitUs (10);
 LPC_EMC->DYNAMICCONTROL = 0x00000083; /* Issue MODE command */

 /* Mode register: Burst Length: 4, Burst Type: Sequential, CAS Latency: 3 */
 WR_MODE(((3 << 4) | 2) << 12);
 // Follow with at least 2 NOPS
 LPC_EMC->DYNAMICCONTROL |= EMC_INIT(EMC_NOP);
 LPC_EMC->DYNAMICCONTROL |= EMC_INIT(EMC_NOP);
 LPC_EMC->DYNAMICCONTROL = 0x00000003; /* Issue NORMAL command */
 LPC_EMC->DYNAMICCONFIG0 |= (1 << 19); /* Enable buffer */
 LPC_EMC->STATICCONFIG0 |= (1 << 19) ; /* Enable buffer */
#endif

<pre class="MsoPlainText">
One further design note: Please use the CLK2 pin for the SDRAM clock, it has a slightly better timing characteristic than the CLK0 pin.
Then you need to configure the CLK23 signal on the CLK2 pin (= func 5). CLK3 pin must be configured to func 0 at the same time.

Best regards,
NXP Technical Support Team

SDRAM configuration

SDRAM configuration

LPC43xx