Content originally posted in LPCWare by dpliu on Mon Mar 25 23:50:29 MST 2013
the configurations which work well:
CAN PCLK=OSC=12MHz,CLKDIV=0,BT=0x2701(BRP=1),
means 500kbps*(2+7+3)*(BRP+1)=12MHz
the configurations which work with problems:
CAN PCLK=PLL1=204MHz,CLKIDV=0,BT=0x2721(BRP=33),
means 500kbps*(2+7+3)*(BRP+1)=204MHz
the configurations which also work with problems:
CAN PCLK=PLL1=204MHz,CLKIDV=5(CAN_CLK=PCLK/17),BT=0x2701(BRP=1),
means 500kbps*(2+7+3)*(BRP+1)=204MHz/17=12MHz
It seems there will be something wrong when use PLL1 as PCLK of CCAN.The CLKDIV(default 0) and the BRP(default 1) can only work with there default values? Or there are some strict order except INIT bit and CCE bit which I have known when configure the registers?