lpcware

CAN Errata on LPC4337

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by otscherw on Wed Aug 06 08:33:19 MST 2014
Hi,

I have a board with an LPC4337FET256 / ESD13450- and have currently some difficulties on getting the CAN1 interface running.
As I understand the Errata Sheet for Revision '-', CAN0 and CAN1 should work reliably, as long as you don't access the conflicting peripherals as DAC, ADC0, ADC1 etc. Is this correct?
Currently I don't use any of those peripherals so I should be safe.

I have a test firmware using LPCopen v2.09  that can send and receive on CAN0, but when I'm trying to switch the same code from CAN0 to CAN1 I still can send messages, but don't receive anything. A receive interrupt is triggered, RXOK bit 4 in status reg is set, but the expected bit in the interrupt register is not set, although message object 2 was set up for receiving (and this works on CAN0).

So I suspect some issue with message filtering. Could of course be some bug in my FW, but before I continue debugging I just wanted to clarify that what I'm trying to do actually works. Or is there some kind of other errata that can explain this behaviour?

EDIT: my code is running from DRAM, if this should be relevant.

And finally, what are NXP's plan for fixing this errata, i.e. when do you ship a new silicon revision?

Regards,
Oliver


Outcomes