Content originally posted in LPCWare by IJeffray on Tue Aug 05 02:58:09 MST 2014
The UM10503.pdf documentation for the LPC43S20 CPU we're using states that the shipped state of the OTP should be all zeroes.
To verify this, I can read OTP3 directly, and see it's all zeroes, which is good. But attempting to read OTP1 or OTP2 causes a fault, which is understandable - these memories are used for storing AES keys which only the ROM routines can access. Good. So in order that I can verify that the device is in the correct shipped state, I encode some data using a software supplied key of all zeroes, then decrypt it using one of the hardware keys. The issue is, the result does not decrypt correctly, meaning that neither of the OTP1 or OTP2 memories is actually zero.
So two questions:
1/ What SHOULD the default state of OTP1 and OTP2 be on LPC43Sxx parts which support encryption, if not zero?
2/ How else may I verify that the OTP memories are received in the correct state on the production line?
