Content originally posted in LPCWare by ganigangi on Fri Oct 25 01:44:20 MST 2013
Quote: biggerfoot
Just read from the news, ADSP-CM40x from ADI runs up to 240Mhz.
Does NXP have a plan for a faster M4?
Hi,
I have already worked on LPC1768
and my program codes was grown till all 512KB of flash was filled
in between because of small 32k+32k bytes of SRAM I was challenging for each code pieces addition
and gradually I encountered the speed limitation ( 100MHZ )
then I planned to migrate to LPC1788 , but it has the same limitation ( 96KB RAM , 120MHZ speed )
I was around to select CM4 such as LPC43xx , but the limitations are the same
flash = 512KB , 1024KB
RAM = 136KB
for my future developments I need
- more than or equal to 2048 KB of FLASH code memory ( 3072MB+ is the best for me )
- more than 256 KB of RAM memory ( 512KB+ is the best for me )
NXP forces me to use flashless CM4 that has more RAM ( 168KB , 200KB , 264KB )
but it should be add external memory and more pcb area
I am confused!
I think there will be a fast growing demand for massive computing power and more larger memory in near future
it is good idea to :
- adding external memory on the top of chip ( 256MB , 512MB , 1024MB SDRAM DDRn )
- increasing core speed to 600MHZ ... 1200MHZ
- adding more cores and didicated RAM for each core (16...256 cores , 32kB for each ) ( from massive FPGA world )
- adding more I/O pins ( 100 ... 1500 pins ) ( from massive FPGA world )
- adding LVDS IO transeciver logic ( from massive FPGA world )
- increasing ethernet speed to 1000
======================================================================
these devices will be massively used in automotive ( 1 ... 5 parts per NEW CAR ) on 2015 and next
( where I and my team and competitors are hardly working on projects that based on massive FPGA but expensive )
and for PLC for Industrial
and on IMAGING for MRI_ULTRASOUND
and for military or industrial RADAR
======================================================================
..........
and it would be great that the chip designers to add hardware's to handle RTOS operations and remove
the " time consuming software overhead" of it
as :
- adding a huge amount of banked registers ( eg: 64 banks of 64word(4bytes) register bank for 64 individual tasks = 64*64*4= 16KBYTES )
( removing the PUSH POP or save and restore on each task
- dedicated RTOS tik timer and a "time plan file" ( a 64 * 2bytes register to define each task "time share" ) + 64*1bytes for priority
- and a connection matrix bus between cores to improve access speed
- and more functional DMA controller to remove any overhead from CPU
it is a large design ......
but the first vendor that will generate this device
will have the huge market share of $10Billion yearly
