Simple dual core application

[lpcware]

Content originally posted in LPCWare by jgorsk on Mon Nov 05 07:36:00 MST 2012
Can somebody share a simple Keil dual core application for flash based LPC43xx?
No RTOS, USB or anything fancy. Just proper Keil configuration, some initialization
functions and two blank main functions, one for M4 and one for M0. All the dual core
examples I found so far are way too complicated for me plus they are missing
files or have errors in the source files and I'm not able to compile them.
I'm new to ARM and Keil and it's very hard to use the dual core feature
using so little documentation available.

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Wed May 21 23:40:58 MST 2014
If you are using LPCXpresso IDE, then we do provide a simple dual core example based on the old Peripheral Driver Library within the Examples directory of your installation, for example for the MCB4357 board. Also for LPCXpresso, I would advise reading...

http://www.lpcware.com/content/faq/lpcxpresso/lpc43xx-multicore-apps

Regards,
LPCXpresso Support

[lpcware]

Content originally posted in LPCWare by Kaveh.Firouzi on Wed May 21 11:12:16 MST 2014
I already have the package. I meant the simpler example project that Bavarian had linked. As the original poster mentioned, the examples in the LPCOpen package are too complicated.

[lpcware]

Content originally posted in LPCWare by lpcxpresso-support on Mon May 19 23:47:00 MST 2014
The multicore examples are in the LPCOpen package for LPC43xx.

[The links provided above were produced >18 months ago for a pre-release version]

[lpcware]

Content originally posted in LPCWare by funkyguy4000 on Mon May 19 18:21:11 MST 2014
bump
and I have the same issue as well.

[lpcware]

Content originally posted in LPCWare by Kaveh.Firouzi on Mon May 19 08:20:51 MST 2014
Hello,

I have the exact same problem as the original poster. The links that you have provided doesn't work anymore, could you please let me know where I can find the simplified dual core project?

Best regards,
Kaveh Firouzi

[lpcware]

Content originally posted in LPCWare by Heikon on Tue Jan 08 05:41:49 MST 2013
yes, that´s it, thank you...

[lpcware]

Content originally posted in LPCWare by wellsk on Fri Jan 04 10:13:00 MST 2013
Snapshots have been disabled on purpose due to some problems/misuse.

You can still pull a snapshot for the latest LPC43xx repo using the following link:
http://sw.lpcware.com/?p=lpc43xx.git&a=snapshot&h=HEAD&fmt=zip

[lpcware]

Content originally posted in LPCWare by Heikon on Fri Jan 04 08:17:07 MST 2013
hey,
can´t get a snapshot, "snapshot disabled" came when I try.
Also n email can be sent, "not accessible"
and the example with the SCT PWM is not availible in the download *.zip file
what did I do wrong???
heiko

[lpcware]

Content originally posted in LPCWare by jgorsk on Thu Nov 22 06:54:57 MST 2012
Thanks for your reply bavarian,

Indeed it's simple to use the dual core feature of the LPC43
once you know how to do that. It's very hard to learn using
the existing documentation.

The biggest problem I had was how to debug the M0 program
in the internal flash memory of the LPC4347. In particular
how to reset M0 CPU. I was using keil debugger. It was really hard
to do properly. The only good enough way I found was to load the
M0 application and don't run it, just set a breakpoint somewhere
at the beginning of the program and run it. Then switch to M4
debugger and force M0 reset there (preferably by resetting the M4 core).
The M0 debugger stops at the breakpoint and works fine since then.

Without setting a breakpoint at the beginning of the M0 program
debugging sometimes didn't work properly, in step mode the CPU jumped
into the middle of the program instead of executing it line by line.
That initially made me think something was wrong with my program
or the debugger. Everything was fine, the debugger just needs
a breakpoint to stop at, otherwise the M0 CPU will keep running
while the debugger is stopped at some line and when a step is made is will
try to catch up with the CPU. Is that how it works?

[lpcware]

Content originally posted in LPCWare by bavarian on Wed Nov 21 10:24:02 MST 2012
See my comments below:


M0 project questions

1.
Target device is generic ARM Cortex-M0. When I start a dual core project from scratch,
should I select the generic M0 or should it be some NXP part?
--> Generic M0

2.
IROM1 start address is 0x18000000, size is 0x200. According to the LPC43 user manual that area
is reserved. IRAM1 and IRAM2 are also in the same reserved area. Should these settings be always
used to the M0 project?
--> I'm pretty sure that this project works with scatter files and not with the settings in the target tab. So whatever is inserted in these fields, it's not used anyway. And 0x1800000 is indeed no SRAM area which can be used.

3.
I am able to build and debug the M0 project alone. Which CPU is used in this case, is it the M4?
--> if you compile for an M0, if you selected the M0 core in the debugger tab, if you start the debugger, then of course you work with the M0.

M4 project questions

4.
Target device for the M4 project is LPC4350, I'm using 4357, should I change the target device
setting to LPC4357?
--> For the compiler this is a don't care. If you select the target from the list of NXP devices you get some pre-settings for memory areas (which you don't need because you work with scatter files) and the registers are listed in the debugger if you like. So change it to LPC4357, ignore the memory areas which are filled into the fields of the target.

5.
There is no IROM defined for the M4 project. Are the IROM settings important at all?
--> same thing: please always check if the memeory areas are defined in this tab or in a scatter file !!!

6.
When the debugger is started for M4 project (LPC43xx_M4_internal_flash target) and then stopped
(the debugger session is ended without executting any lines in the program) it cannot be restarted.
The error message is "ULINK - Cortex-M Error. Could not stop Cortem-M device! Please check the JTAG cable".
To restore the debugger operation I need to change the boot config pin state and reset CPU. Why is it happening
every time and how to correct that? In my application P2_7 is high - boot from internal flash.
There is something in platformInit() function that may be causing this but it also happens when that function is commented out.
Best case I am able to start debugging but the program will crash eventually
--> I will check the SW package. Most likely related to the debugger ini scripts

7.
When the LPC43xx_M4_RAM target is selected the M4 project cannot be built due to "!!! M0_ROM_START
not defined, check platform_init.h !!!" error. How to correct that?
--> I will check the SW package.

8.
Sometimes the debugger will not start due to a Memory Mismatch at address 0x1A000004, value 0x9D, expected 0x89.
Manually downloading to flash solves this problem.
--> no idea

Is there a document avaliable which describes how to do a dual core project step by step?
--> No, not yet. But I think it's worthwhile to do it.
But here are some basic thoughts:
- The M4 always starts up the LPC43xx, the M0 is in reset state.
- When the M4 is in its execution area (e.g. the ResetHandler or later) it must provide the start address
  for the M0 code to the M0, before taking it out of reset state. Otherwise the M0 runs into HardFaults.
- Again, the M4 is always responsible for setting up the chip and prepare the ground for the M0.
- The M4 and the M0 can execute from any memory region, the way you create the binaries for the respective regions
  (linker settings of your M4/M0 projects) and the method you use to program them is fully up to you.
  e.g. M4 code in flash bank #A, M0 code in flash bank #B
    o create M0 image, integrate it into M4 image, program it into flash as one image
    o create M4 image, program it into flash bank #A, create M0 image, program it into flash bank #B
  e.g. M4 code in flash bank #A, M0 code runs from SRAM
    o create M0 image, integrate it into M4 image, program it into flash as one image, the M4 will relocate the M0 image after
      startup from flash into the SRAM execution region (specified by you) for the M0

As you can see there are various ways to set this up, important is to understand the basics, specify the memory map for your own
application and then realize it in your toolchain.
Debugging is a little bit more tricky, because it depends on the debugger hardware/software. But if you either debug the M0 or
the M4 then it should work fine with the common solutions.

Regards,
NXP Technical Support Team

[lpcware]

Content originally posted in LPCWare by jgorsk on Tue Nov 06 13:03:53 MST 2012
I managed to modify the source code so the example now works on my custom board.
The only thing I can't get to work is the debugging of the M0 C program. I can
only set breakpoints or run the program in step mode in the assembly code.
This is when 'Load application at startup' setting is not selecting. When it is selected
the M0 debug session will not start.

What should the debugger setting be for the M0 project?

[lpcware]

Content originally posted in LPCWare by jgorsk on Tue Nov 06 02:59:56 MST 2012
Thanks for your reply bavarian,

This dual core example is fairly simple but a few things aren't clear to me.
Could you answer the following questions please?

M0 project questions

1.
Target device is generic ARM  Cortex-M0. When I start a dual core project from sratch,
   should I select the generic M0 or should it be some NXP part?

2.
IROM1 start address is 0x18000000, size is 0x200. According to the LPC43 user manual that area
   is reserved. IRAM1 and IRAM2 are also in the same reserved area. Should these settings be always
   used to the M0 project?

3.
I am able to build and debug the M0 project alone. Which CPU is used in this case, is it the M4?



M4 project questions

4.
Target device for the M4 project is LPC4350, I'm using 4357, should I change the target device
   setting to LPC4357?

5.
There is no IROM defined for thr M4 project. Are the IROM settings important at all?

6.
When the debugger is started for M4 project (LPC43xx_M4_internal_flash target) and then stopped
   (the debugger session is ended without executting any lines in the program) it cannot be restarted. 
The error message is "ULINK - Cortex-M Error. Could not stop Cortem-M device! Please check the JTAG cable".
To restore the debugger operation I need to change the boot config pin state and reset CPU. Why is it happening
every time and how to correct that? In my application P2_7 is high - boot from internal flash.
There is something in platformInit() function that may be causing this but it also happens when that function is commented out.
Best case I am able to start debugging but the program will crash eventually

7.
When the LPC43xx_M4_RAM target is selected the M4 project cannot be built due to "!!! M0_ROM_START
   not defined, check platform_init.h !!!" error. How to correct that?

8.
Sometimes the debugger will not start due to a Memory Mismatch at address 0x1A000004, value 0x9D, expected 0x89.
Manually downloading to flash solves this problem.


Is there a document avaliable which describes how to do a dual core project step by step?

[lpcware]

Content originally posted in LPCWare by bavarian on Mon Nov 05 11:00:22 MST 2012
Hello,

look here and take a snapshot:

http://sw.lpcware.com/index.php?p=lpc43xx.git&a=summary

-  In Examples go to DUALCORE\Int_Demo\Keil and use the multi project file M4_M0_ipc.uvmpw.
-  This includes the M0 project and the M4 project.
-  Right mouse click on the M0 project --> Set as Active Project --> Build
-  Right mouse click on the M4 project --> Set as Active Project --> Build
-  At least for me everything is there and it compiles fine
-  Flash the result with ULINK2

The default config puts the M0 image in flash bank #B (see link-CM0_flash.sct) and the M4 image in flash bank #A (see link-M4_internal_flash.sct). The M4 executes from bank #A and the M0 from bank #B, each with an own bus, so they don't interfere with other on code execution.
The example could be simpler, but there is not much overhead, just a small framework for master (M4) and slave (M0). That's just a definition, nothing else.
You could deal with the M4 and M0 projects independently, using the project files M4.uvproj and M0.uvproj, but the multi project file is really handy.

Regards,
NXP Tech Support Team