LPC4350A_PDL and M0

[lpcware]

Content originally posted in LPCWare by charchar on Thu Jan 12 15:38:10 MST 2012
The new LPC4350A_PDL sofware/example package is great--- lots of great examples, but it seems to be lacking a dual core example.  Mostly, I'd like an example that uses both cores (M4 and M0) and allows me to debug code running on either core.

are there examples available or in the works?

thanks!

 

[lpcware]

Content originally posted in LPCWare by PhilYoung on Mon Apr 09 12:34:32 MST 2012
I've been playing around with startup code for this and found there are a few benefits of doing things slightly different to the way the examples work.
The example code builds the application as a single binary including both the M0 and M4 code, which requires re-flashing the entire code and re-building the M4 app each time the M0 project is updated.
This creates a bootable image for the M0 but is inefficient as the image must be de-compressed and copied to RAM to be executed, generally it's better simply to build an M0 bootable image to be executed from flash so that the ram footprint is much smaller, this also allows the boot loader code to remain in flash further reducing the memory overhead as only the important application code needs to be copied to SRAM for speed.

To achieve this I simply create a scatter load file which sets the load and execute address for the M0 startup code at a fixed address in flash which is known to the M4 app, the M4 then simply sets the shadow address of the M0 memory to the base address of the M0 image in flash and lets the M0 do all of the init code, this allows the compressed const data and code to be de-compressed directly from flash to the required execute address.

It also allows the M0 image to be flashed without erasing the M4 image, and allows the M4 to perform runtime updates of the M0 image.

Additionally, the method used in the examples to build a data structure generates a compressed image and requires to de-compress this since the table containing the M0 image is defined as unsigned char LR0[], i.e. it is not const so cannot reside in flash. It's better to include this file into the main M4 image if this is required by using a simple file that changes the type to const and exports the symbol. I simply have a file containing 2 lines
extern const
#include "LR0.h"
where LR0.h is the file generated by the M0 project. This changes the type of LR0 to const, i.e. +RO instead of the default +RW.

The M4 image then simply places LR0 in a section at 0x1c040000 allowing it to be overwritten independantly of the M4 code.

[lpcware]

Content originally posted in LPCWare by Massimo Manca on Sat Mar 17 02:06:25 MST 2012
You could also download my project example. It works on the Hitex board. There is a simple communication mechanism between the 2 cores and a simple security mechanism implemented as an heartbeat message.

[lpcware]

Content originally posted in LPCWare by charchar on Mon Jan 16 10:32:28 MST 2012
Some notes regarding this example:

If you want to run it from RAM, you need to change line 85 in the m4 main.c from

IPC_downloadSlaveImage(SLAVE_ROM_START, &LR0[0], sizeof(LR0));

to

IPC_downloadSlaveImage(SLAVE_RAM_START, &LR0[0], sizeof(LR0));

or it will crash (hardfault).

[lpcware]

Content originally posted in LPCWare by charchar on Fri Jan 13 12:52:16 MST 2012
I must have downloaded an earlier version.  I see it in the posted zip file--- thanks!

[lpcware]

Content originally posted in LPCWare by atomicdog on Fri Jan 13 10:35:47 MST 2012
I see a project under examples/DUALCORE.

The abstract.txt says...

Purpose:
This example demonstrates inter-processor communication between the Cortex-M4
and Cortex-M0 cores in the LPC4350 CPU.