lpcware

LPC43xx:  EMC (SDRAM), GPDMA

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by mch0 on Thu Apr 17 08:23:35 MST 2014
Hello,

is there any document other than the UM that explains in more detail the operation of the EMC when operating in SDRAM mode?
I'm trying to calculate the bus saturation (internal and from the LPC to the SDRAM) when moving samples from the ADCHS to SDRAM.
For this I would like to understand how the EMC buffers write data and whether it combines write bursts to the same page (row) of the SDRAM.
The UM mentions four buffers, each containing 16 words and that the EMC will do (only!) burst transactions of 4 words. The latter is a bit surprising (does it really write 4 words if I'm going to write a single byte?. Yes, technically feasible, but would involve 3 write transactions with all DQM inactive ..).
However, for my application bursts of 4 are nice enough.
The UM also says a bit about when the EMC will flush a buffer. Yet I miss some information or simply look in the wrong place:

- If a buffer contains more than 4 words at "flush time": Does the EMC produce back-to-back write bursts or does it produce several "self contained" bursts like: activate row -> write burst -> precharge?
- are these 4 buffers statically allocated to the four DYCS regions or can the EMC use all 4 buffers on a single SDRAM (DYCS), if there is only one?
- can I somehow "help" the EMC to produce the most effective sequence of SDRAM transactions by filling the buffers in certain way?

Likewise I would like to understand the speed of the GPDMA, especially arbitration issues, better.
How many cycles does the GPDMA require for arbiration when the AHB is idle (hopefully at most 1)?
I understand that it is not a fly-by DMA from ADCHS to the EMC but uses a read to FIFO, write from FIFO approach (like flow-through), thus requiering 2 cycles per transfer minimum.
Since the FIFO seems to have 4 words: if I program a burst size of 8, will it do 4 source reads to fill the FIFO, followed by 4 destination writes and then repeate that sequence a second time or will it read/write 8 times in succession, as long as source and destination are availabe at request time?

If there are documents explaining these kind of items I'd be happy to read them ...

Regards,

Mike

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