shadow memory area bug?

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by PhilYoung on Mon Sep 03 05:32:39 MST 2012
Has anybody found out exactly how the shadow registers work (M4MAP,M0APPMAP).
The documentation indicates that they remap the bottom 256MB Shadow area base address, but if so then they don't work properly.

I've built an image to run at 0x0, loaded it into flash at 0x1c000000 and also 0x1c040000, in both cases it runs when I set the proper shadow address in M4MAP
if I load the same valid image at 0x1c020000 and set M4MAP accordingly it no longer runs.

single stepping the code it crashes in the ARM startup code during the decompress stage.
It turns out that with this address mapping only part of the image if visible, and part of it is garbage.

If I set the M4MAP to 0x1c000000 I can view and verify the valid image at 0x2000, but when I set the M4MAP to 0x1c020000 only half of the image is visible and correct, the other half is garbage.

It seems as though the LSB set in M4MAP determines the usable size of the Shadow area, anything above this is invalid, but this is NOT mentioned anywhere in the datasheet.

The same behaviour occurs with M0APPMAP, and if you set memory view windows from both processors you can see that the memory is not accessed correctly when the base address is above the LSB of the corresponding MAP register.