lpcware

LPC4330 PLL issues whith RAM run&debug.

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by aozima on Sat Aug 29 02:33:23 MST 2015
When I change the project to  ram debug, app can not startup.

step by step from Reset_Handler,

if (core_freq > 110000000UL) {
/* Setup PLL for 100MHz and switch main system clocking */
Chip_Clock_SetupMainPLLHz(clkin, CGU_IRC_FREQ, 110 * 1000000, 110 * 1000000);
Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false);
}

==>

void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn)
{
LPC_CGU->BASE_CLK[BaseClock] = reg; // fault here

// add the delay test OK
{
volatile uint32_t i;
for(i=0; i<1000000; i++);
}

}


But the AUTOBLOCK is enable.

why?

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