if (core_freq > 110000000UL) { /* Setup PLL for 100MHz and switch main system clocking */ Chip_Clock_SetupMainPLLHz(clkin, CGU_IRC_FREQ, 110 * 1000000, 110 * 1000000); Chip_Clock_SetBaseClock(CLK_BASE_MX, CLKIN_MAINPLL, true, false); } ==> void Chip_Clock_SetBaseClock(CHIP_CGU_BASE_CLK_T BaseClock, CHIP_CGU_CLKIN_T Input, bool autoblocken, bool powerdn) { LPC_CGU->BASE_CLK[BaseClock] = reg; // fault here // add the delay test OK { volatile uint32_t i; for(i=0; i<1000000; i++); } } |