Need explanation of some SGPIO registers

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by tantalos on Fri Oct 02 05:25:26 MST 2015
Hello, I need some explanation of the function of the following bits in register SLICE_MUX_CFG, because the datasheet is very vague about this:
- CLK_CAPTURE_MODE, is it used to select the clock edge which captures the data on the DIN pin? Does this bit also change the clock edge that shifts the data out on DOUT pin?
- INV_OUT_CLK what is the function of this bit ?

I have written a small program, that outputs slice L clock on pin SGPIO15, and slice N dout on SGPIO11 in simple 1 bit mode. On the oscilloscope I see that the data on the SGPIO11 is shifted on the falling clock edge of SGPIO15. Can the clock edge be changed? Also I'd like to know which clock edge is used to capture the data on pin DIN of slice N.