Need explanation of some SGPIO registers

[lpcware]

Content originally posted in LPCWare by tantalos on Fri Oct 02 05:25:26 MST 2015
Hello, I need some explanation of the function of the following bits in register SLICE_MUX_CFG, because the datasheet is very vague about this:
- CLK_CAPTURE_MODE, is it used to select the clock edge which captures the data on the DIN pin? Does this bit also change the clock edge that shifts the data out on DOUT pin?
- INV_OUT_CLK what is the function of this bit ?

I have written a small program, that outputs slice L clock on pin SGPIO15, and slice N dout on SGPIO11 in simple 1 bit mode. On the oscilloscope I see that the data on the SGPIO11 is shifted on the falling clock edge of SGPIO15. Can the clock edge be changed? Also I'd like to know which clock edge is used to capture the data on pin DIN of slice N.

[lpcware]

Content originally posted in LPCWare by tantalos on Tue Oct 06 04:18:16 MST 2015
I have found in the datasheet how it works
"Each time COUNT reaches zero the register shifts right; loading bit REG[31] with data
captured from DIN and loading DOUT with bit REG[0]. Thus COUNT controls the serial
data rate. When several slices are used to create an interface port the phase between the
different slices can be controlled by using different initial COUNT value."
But still I don't know what are the bits CLK_CAPTURE_MODE and INV_OUT_CLK in the register SLICE_MUX_CFG for.