lpcware

SGPIO inverted clock qualifier

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by pdv on Sun Feb 15 10:18:17 MST 2015
Hi,

With bits 6:5 of SGPIO_MUX_CFG the QUALIFIER_MODE is selected (0x0=enable, 0x1=disable, 0x2=slice, 0x3=pin).
With bit 8 (INV_QUALIFIER) of SLICE_MUX_CFG one can invert the qualifier (0x0=normal qualifier, 0x1=inverted qualifier).

However if one sets INV_QUALIFIER=0x1, then the meanings of the first 2 alternatives of the QUALIFIER_MODE are reversed, in other words: 0x0=disabled and 0x1=enabled.

I've tested this with a pin-qualifier using the LPC4330-Xplorer board.

Regards,

pdv

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