SGPIO inverted clock qualifier

[lpcware]

Content originally posted in LPCWare by pdv on Sun Feb 15 10:18:17 MST 2015
Hi,

With bits 6:5 of SGPIO_MUX_CFG the QUALIFIER_MODE is selected (0x0=enable, 0x1=disable, 0x2=slice, 0x3=pin).
With bit 8 (INV_QUALIFIER) of SLICE_MUX_CFG one can invert the qualifier (0x0=normal qualifier, 0x1=inverted qualifier).

However if one sets INV_QUALIFIER=0x1, then the meanings of the first 2 alternatives of the QUALIFIER_MODE are reversed, in other words: 0x0=disabled and 0x1=enabled.

I've tested this with a pin-qualifier using the LPC4330-Xplorer board.

Regards,

pdv

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Fri Feb 20 18:59:50 MST 2015
The observed behavior is indeed the case.
With bits 6:5 of SGPIO_MUX_CFG the QUALIFIER_MODE is selected (0x0=enable, 0x1=disable, 0x2=slice, 0x3=pin).
With bit 8 (INV_QUALIFIER) of SLICE_MUX_CFG one can invert the qualifier (0x0=normal qualifier, 0x1=inverted qualifier).
However if one sets INV_QUALIFIER=0x1, then the meanings of the first 2 alternatives of the QUALIFIER_MODE are reversed, in other words: 0x0=disabled and 0x1=enabled.
Technically the qualifier_mode
-0x0 makes the qualifier continues 1,
-0x1 makes it continues 0,
-0x2 ..
-0x3 ..
The inversion turns the 1 into 0 and the 0 into 1 causing the strange observation.
regards,

[lpcware]

Content originally posted in LPCWare by JohnR on Thu Feb 19 06:52:09 MST 2015

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Quote:

I've used a /CS signal from another slice as a qualifier for an SPI clock, for reading data from an ADC with two data lines. That worked nicely. (The qualifier enables the clock, in case that is your question?)

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Yes, that's exactly what I did in my system, except that I toggled a spare GPIO pin rather than using another SGPIO channel.

If NXP were thinking of redesigning the SGPIO system, the ability to reverse the counter direction would be wonderful in handling inputs that were either MSB- or LSB-first.

JohnR

[lpcware]

Content originally posted in LPCWare by starblue on Thu Feb 19 02:15:31 MST 2015

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Quote: JohnR

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Quote: starblue

While you are at it, it would be nice if you could clean up Figure 43 "Basic operation of one slice" w.r.t. qualifier and clock selection.

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Could you please expand on that sentence? Having got SGPIO working more or less by trial and error, I would be interested in knowing more about its operation.

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If in Figure 43 you look at the 4-way multiplexer for the clocks with the single input labeled "qualifier" and compare it to the register description, it just doesn't make sense.  IMHO there need to be separate multiplexers for clock and qualifier selection, maybe in a separate figure.

I've used a /CS signal from another slice as a qualifier for an SPI clock, for reading data from an ADC with two data lines. That worked nicely. (The qualifier enables the clock, in case that is your question?)

[lpcware]

Content originally posted in LPCWare by JohnR on Wed Feb 18 07:05:58 MST 2015
Hi Starblue

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Quote: starblue

While you are at it, it would be nice if you could clean up Figure 43 "Basic operation of one slice" w.r.t. qualifier and clock selection.

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Could you please expand on that sentence? Having got SGPIO working more or less by trial and error, I would be interested in knowing more about its operation.

Thanks

JohnR

[lpcware]

Content originally posted in LPCWare by starblue on Wed Feb 18 01:52:09 MST 2015
While you are at it, it would be nice if you could clean up Figure 43 "Basic operation of one slice" w.r.t. qualifier and clock selection.

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Tue Feb 17 13:44:22 MST 2015
thanks, pdy.
We will check and clarify this.