How to find the correct timming values for the SDRAM controller

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by larsjep on Wed Oct 03 08:09:59 MST 2012

I having some trouble understanding how the timming values are calculated.

If I look in lpc43xx_emc.c (from the PDL) line 198, there is a comment saying: "// calculated from xls sheet"

Is this xls sheet available somewhere ?

Ex. if I look at the value for DYNAMICRP it is set to 1. (in lpc43xx_emc.c line 198)
This should give a tRP of 2xCLK = 19.6ns (When running at 102Mhz)
But the datasheet for the SDRAM on the Hitex board states minimum 20ns (-7 speed)

Shouldn't the DYNAMICRP be set to 2 then ?
Or should the EMC_CLK_DELAY also be involved in the calculation ?

Also the DYNAMICRAS seems incorrect. This is set to 3 => 39.2ns, but the datasheet for the RAM states minimum 42ns

Best regards