Recommended use of AUTOBLOCK bit in CGU registers

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by hangdog on Fri Jun 12 04:09:55 MST 2015

I've just debugged a nasty fault in my LPC43xx project, and I wanted to share how I ended up there, and ask if there is a way to make it less easy for others to end up there in future. I'm looking at UM10503 Rev 1.9, and it didn't set me right; did I miss the information I needed, or is the UM missing it?

I was setting CGU_BASE_PERIPH_CLK to a value of just (0x09 << 24) which sets the source to PLL1 (UM Table 143, page 183-4). I was then, pretty much immediately afterwards, attempting to write one of the registers in the SGPIO peripheral. The write was, occasionally, failing to take, and the peripheral as a result was not functioning. I established that leaving a physical time delay between the clock change and the write eliminated the problem. I later discovered that setting the AUTOBLOCK bit in CGU_BASE_PERIPH_CLK also eliminated it. Ok, that all makes sense, I can see what is probably happening there.

Only, the UM does not anywhere seem to indicate under what circumstances I should set or clear AUTOBLOCK. Nor does it indicate what might happen, physically, if I do or do not set the bit. In addition, it states explicitly that "No special requirements exist for ... changing any of the peripheral base clocks either from low to high or from high to low frequencies." (page 158) which seems misleading, given the above.

Would a statement to the effect "always use AUTOBLOCK" be fair? Or are there conditions under which I should not use it? Is this information in the UM, and I've missed it? Or is it in some generic manual that I haven't found?

Thanks for any thoughts