lpcware

LPC4337 Flash Bank B can not be programmed

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Alex on Wed Feb 06 01:58:39 MST 2013
Hi,

I'm currently trying to set up a dual core application on the LPC4337. The M4 code will be stored in Flash Bank A and the M0 code in Flash Bank B.

I'm using JLink and IAR EWARM 6.5 to flash and debug the applications.

The M4 code can be flashed without any problems but the M0 code can not be written to Flash Bank B. The JLINK driver reports verification errors after flashing. There is one strange thing: The debugger says "Core is locked up!" when flashing the M0 project. Maybe this is the cause?

Then I tried Segger JFlash. The same here writing to Bank B is not possible. Reading the Bank is no problem.

Or possibly the JLINK debugger probe is too old? It is version 6.0 from 2009...

Here is what the IAR debugger says:
Wed Feb 06, 2013 09:55:02: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\NXP\FlashNXPLPC18xx.mac
Wed Feb 06, 2013 09:55:09: JLINK command: ProjectFile = C:\Users\.........\Software\NXP_TRAINING\M0_src\settings\NXPTrainingM0_Debug.jlink, return = 0
Wed Feb 06, 2013 09:55:09: JLINK command: scriptfile = C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\LPC4350_DebugCortexM0.JLinkScript, return = 0
Wed Feb 06, 2013 09:55:09: Device "LPC4337_M0" selected (0 KB flash, 0 KB RAM).
Wed Feb 06, 2013 09:55:09: DLL version: V4.62a, compiled Feb  4 2013 11:51:03
Wed Feb 06, 2013 09:55:09: Firmware: J-Link ARM V6 compiled Jun 20 2012 19:43:26
Wed Feb 06, 2013 09:55:09: JTAG speed is initially set to: 32 kHz
Wed Feb 06, 2013 09:55:09: NXP LPC4350 (Cortex-M4+M0 core) J-Link script
Wed Feb 06, 2013 09:55:09: TotalIRLen = 8, IRPrint = 0x0011
Wed Feb 06, 2013 09:55:09: TotalIRLen = 8, IRPrint = 0x0011
Wed Feb 06, 2013 09:55:09: Found Cortex-M0 r0p0, Little endian.
Wed Feb 06, 2013 09:55:09: FPUnit: 2 code (BP) slots and 0 literal slots
Wed Feb 06, 2013 09:55:11: J-Link script: Performing reset sequence
Wed Feb 06, 2013 09:55:11: Core is locked-up!
Wed Feb 06, 2013 09:55:11: CPU halted
Wed Feb 06, 2013 09:55:11: Hardware reset with strategy 0 was performed
Wed Feb 06, 2013 09:55:11: Initial reset was performed
Wed Feb 06, 2013 09:55:11: Found 2 JTAG devices, Total IRLen = 8:
Wed Feb 06, 2013 09:55:11:  #0 Id: 0x4BA00477, IRLen:  4, IRPrint: 0x1 CoreSight JTAG-DP
Wed Feb 06, 2013 09:55:11:  #1 Id: 0x0BA01477, IRLen:  4, IRPrint: 0x1 CoreSight SW-DP
Wed Feb 06, 2013 09:55:11: ------- Prepare for flashloader -------
Wed Feb 06, 2013 09:55:11: 1504 bytes downloaded and verified (5.54 Kbytes/sec)
Wed Feb 06, 2013 09:55:11: Loaded debugee: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\flashloader\NXP\FlashNXPLPC18xx_RAM40K.out
Wed Feb 06, 2013 09:55:11: Target reset
Wed Feb 06, 2013 09:55:12: Core is locked-up!
Wed Feb 06, 2013 09:55:12: CPU halted
Wed Feb 06, 2013 09:55:12: Downloaded C:\Users\.........\Software\NXP_TRAINING\M0_src\Debug\Exe\cpp.out to flash memory.
Wed Feb 06, 2013 09:55:12: Loaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 6.5\arm\config\debugger\NXP\Trace_LPC18xx_LPC43xx.dmac
Wed Feb 06, 2013 09:55:12: J-Link script: Performing reset sequence
Wed Feb 06, 2013 09:55:12: Hardware reset with strategy 0 was performed
Wed Feb 06, 2013 09:55:12: 4960 bytes downloaded into FLASH and verified (4.19 Kbytes/sec)
Wed Feb 06, 2013 09:55:12: Warning: 
Verify error at address 0x1B000000, target byte: 0xFF, byte in file: 0x08
Wed Feb 06, 2013 09:55:12: Warning: 
Verify error at address 0x1B000001, target byte: 0xFF, byte in file: 0x20

Best regards,
Alex

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