LPC43XX frequently switching BASE_M4_CLK

[lpcware]

Content originally posted in LPCWare by kollesok on Thu Jun 11 06:26:25 MST 2015
Hello,

I wonder if it's ok to periodically switch BASE_M4_CLK between frequency ranges (low - medium - high). My task is not to save as much power as possible, but to reduce the overall heat dissipated by the MCU.
I have developed a High-Speed USB peripheral device with LPC4323, it periodically does an intensive work at a maximum core frequency 204MHz, the rest of the time it just waits for incoming data.
It's a waste to leave the core at that fequency all the time, I have made some measurements, my device consume about 170 mA while waiting. If I reduce the  BASE_M4_CLK down to 48 MHz, the current drops down to 80 mA.
I am not concerned about the efficiency, it's the heat that bothers me, the MCU is really hot when working constantly ay 204MHz.

So, the idea is to have the BASE_M4_CLK at 48MHz while the device is idle and step up to 204 MHz on starting the calculations. But, these transitions might be quite frequent, let's say once every 5 seconds.

Has anyone done anything like that? Are there any pitfalls, unstable behavior of the core or some other implications?

Thank you.

[lpcware]

Content originally posted in LPCWare by kollesok on Fri Jun 12 04:44:29 MST 2015
Yes I have, but it doesn't help much.
The MCU waits for transactions in a loop like this:

    while (1) {
        __asm volatile ("wfi");
        pollUSB();
    }

Putting a core into sleep saves about 20mA, there are periodic USB status events all the time, so the core is actually busy processing non-critical stuff.
My point is to use the highest BASE_M4_CLK frequency only when it's really necessary. The BASE_M4_CLK is not just for M4 core, but also for the APB peripheral blocks #0 and #2.

[lpcware]

Content originally posted in LPCWare by wmues on Fri Jun 12 02:20:15 MST 2015
Have you checked to use the WFI instruction to put the CPU into sleep mode?