USART Baudrate 8 MBit @ 204MHz

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USART Baudrate 8 MBit @ 204MHz

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Fri Apr 18 03:59:19 MST 2014
Running the LPC4357 at 204 MHz, I would like to use the USART with 8 MBaud (this is the max. baudrate according to the datasheet). So far I failed to generate this baudrate. USART clock is connected to PLL1, which is also 204 MHz.

At first I tried to use the following baudrate settings:
define B8M_DLL         1
define B8M_DLM         0
define B8M_DIVADDVAL   7
define B8M_MULVAL      12

These values look fine at first glance. According to the formula given in the user manual in chapter "39.6.12 USART Fractional Divider Register", this should result in a baudrate of 8.0526 MBaud. However, it does not work. I assume that the problem is this tiny note given in the same chapter: "Important: If the fractional divider is active (DIVADDVAL > 0) and DLM = 0, the value of
the DLL register must be 3 or greater."

I tried to find any other combination of the register values, which allows to generate the 8 MBaud form the 204 MHz PLL. But there isn't any combination available. The fastest values I got were 6.375 MBaud, which works reliably. I also tried 12.75 MBaud, which also works without any problems, but it is out of specification.

Is there any way to get the 8 MBaud running at 204 MHz? Or do I need an external clock of 128 Mhz at GP_CLKIN to get the 8 MBaud running? Is there any other way?

Thanks in advance,
Holger


P.S. Please no advices to use USB or something similar. I need the UART interface.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Tue May 06 03:47:44 MST 2014

Quote: starblue

I don't think so, the use of the USB PLL is very limited (see Table 120 "Clock sources for output stages").




Yes, you are right.

Thanxs anyway,
Holger
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by starblue on Tue May 06 02:52:36 MST 2014

Quote: hlsa
(I think I could also use the USB-PLL, but I did not try this.)



I don't think so, the use of the USB PLL is very limited (see Table 120 "Clock sources for output stages"). Though maybe it would be possible via an external pin.


Glad it works

Jürgen
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Mon May 05 22:25:05 MST 2014
It works!
As suggested by starblue, I configured PLL0AUDIO to generate 128 MHz. Further I configured the USART interface to use the PLL0AUDIO as clock source. See attached code snippet for details.
(I think I could also use the USB-PLL, but I did not try this.)

By the way: there is a nice tool available from NXP, which supports configuring the PLL:

http://www.lpcware.com/content/nxpfile/audio-pll-settings-calculation-tool

Thanxs,
Holger
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Tue Apr 29 09:22:46 MST 2014
@starblue

That is indeed a great idea. I will have a look, if the PLL0AUDIO allows generating 128 MHz.

Best regards,
Holger
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by starblue on Tue Apr 29 01:09:10 MST 2014
It seems you can use PLL0AUDIO to generate your UART peripheral clock, have you looked into that?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Mon Apr 28 23:06:09 MST 2014
Hello Packman,

at 192 Mhz the problem remains the same. It would require the following values:

define B8M_DLL 1
define B8M_DLM 0
define B8M_DIVADDVAL 7
define B8M_MULVAL 15

Hence the golden rule from the user manual is broken again.


In a different thread, I asked about the maximum UART baudrate of the LPC4357:
http://www.lpcware.com/content/forum/max-uart-baurate-lpc4357

I asked this to avoid any design mistakes by me, since a high baudrate is extremely important to me. NXP confirmed, that the max baudrate is 8 MBit.
As it looks like, this can only be achieved by an external clock.

Before doing a redesign of our hardware (which costs a lot of money), I would like to get a confirmation, that my understanding of the baudrate calculation is correct. This helps me to avoid a useless redesign.
It looks like I am the first developer using the 8 MBit. However, at least NXP must have used it before and they should know how to do the right settings.


Best regards,
Holger

Best regards,
Holger
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Pacman on Mon Apr 28 10:02:13 MST 2014
128 MHz... I was thinking: 128 MHz would be 2/3 of 192MHz, so it would come out almost "clean", especially if 64MHz is enough.
Did you try that already ?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Mon Apr 28 08:33:32 MST 2014
@starblue:

I could also run at 200 MHz. But as far as I understand the user manual, this does not save my problem. I would need 128 Mhz, which is far too slow.

All other required data rates (CAN, SPI, I²C, ...) have not been a problem for me.

Best regards,
Holger
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by starblue on Mon Apr 28 02:02:11 MST 2014
Do you really need to run at 204 MHz?

It is a lot easier to get the various maximal data rates from 200 MHz (which is what we do, e.g. to get a 20 MHz SPI clock).
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by Pacman on Mon Apr 28 01:47:07 MST 2014
First of all: I have no clue, but I'd really like to answer this question if I could. ;)
Second: Make sure you use the external clock crystal, otherwise you'll probably never get the clock precise enough.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by hlsa on Sun Apr 27 23:27:42 MST 2014
It looks like I need to ask a different way:

I assume that the 8 MBit Baudrate has been qualified by NXP in some way. So: how has this been done? How about the clock used? How about the baudrate settings?

Best regards,
Holger
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