Interrupt Handling

[lpcware]

Content originally posted in LPCWare by krrish on Wed Jul 16 21:40:31 MST 2014
Please any one explain the flow of interrupt handling in lpc43xx.

Thanks in advance.

[lpcware]

Content originally posted in LPCWare by mc on Fri Jul 18 15:17:35 MST 2014
Hi Krrish,
LPC43xx contains Cortex M4 and M0. Please read NVIC chapter from below link
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0553a/BABEDCBC.html
and LPC43xx user manual at
http://www.nxp.com/documents/user_manual/UM10503.pdf

[lpcware]

Content originally posted in LPCWare by whitecoe on Thu Jul 17 01:25:46 MST 2014
Replacing "lpc43xx" in your search with "cortex" would probably be a sensible thing to do. The interrupt model is basically just the standard ARM Cortex-M3/M4 one (or M0 for the M0 cpu on LPC43xx) - and there is a huge amount of info out there on this.

HTH!

[lpcware]

Content originally posted in LPCWare by TheFallGuy on Thu Jul 17 01:06:00 MST 2014
http://lmgtfy.com/?q=interrupt+handling+in+lpc43xx