LPC4357 Internal EEPROM reading problem

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LPC4357 Internal EEPROM reading problem

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by boscfab on Mon Mar 02 02:51:20 MST 2015
Hi,
sometime, after the power-up sequence, the first reading operation in to internal EEPROM fails.
The write procedure it's ok.

I use LPC4357 clocked at 204MHz and the EEPROM setup is this:

unsigned char Init_IIB(uint32_t eepromHz)
{
unsigned char strread[4];
LPC_EEPROM->PWRDWN = 0x0;
/* EEPROM is automate turn on after reset */
/* Setting clock:
  * EEPROM required a 1500kHz. This clock is generated by dividing the
  * system bus clock.
  */
  //eepromHz/=2;
Delay(10);  //10ms
  LPC_EEPROM->CLKDIV = eepromHz / (EEPROM_CLOCK_DIV-1); // 31 ; //EEPROM clock=1500 KHz
  LPC_EEPROM->RWSTATE = (eepromHz / 28571429 + 1) | ((eepromHz / 14285714 + 1) << 8); //(0x3 | 0x5<<8); // Read waitstates.
  LPC_EEPROM->WSTATE = ((eepromHz / 50000000 + 1) << 16) | ((eepromHz / 25000000 + 1) << 8) | (eepromHz / 100000000 + 1); // (0x2 | 0x3<<8 | 0x2<<16); //EEPROM wait state register
  LPC_EEPROM->AUTOPROG = EEPROM_AUTOPROG_AFT_1WORDWRITTEN;//01 = erase/program cycle is triggered after 1 word is written
Delay(10);  //10ms

{
  volatile unsigned char *pchar;
  pchar = (uint8_t*)(EEPROM_START + (126*32*4)-0x100);

  if(pchar[0]==0xAA && pchar[1]==0x55 && pchar[2]==0xAA && pchar[3]==0x55)          \\Check signature EEPROM
   return TRUE;
}
return FALSE;

For testing this problem i check the signature at power up (0xAA, 0X55, 0xAA, 0x55).
Sometime during after the power up the signature check return all 0xFF.....strange!
If i make a loop for the signature check, after some cycle, the result it's ok.

Do you have suggestions?
I added the wait state in RPHASE read and write but nothing changes.

Thanks,

Fabio
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by namorada on Thu Jun 04 06:52:44 MST 2015
Hi,

I'm a bit confusing for disturbing you....
I'm trying, as well, to observe that thing. By the way, it seems doesn't work for me. Is it possible to publish your read/write functions of EEPROM?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by laogan666 on Wed Apr 22 17:10:53 MST 2015
NO,I think the code LPCOPEN is wrong in the configuration of the wait state of reading and writing,before I'm not sure about that.So i want to know the answer.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by boscfab on Wed Apr 22 00:29:53 MST 2015
You have a problem during the reading phase similar to mine?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by laogan666 on Tue Apr 21 18:41:10 MST 2015
Thank you very much.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by boscfab on Tue Apr 21 05:56:33 MST 2015
I received support from NXP FAE but the causes of reading error during the initial phase are not clear.
He confirmed to me that the code LPCOPEN is wrong in the configuration of the wait state of reading and writing.
Concerning my application (it works at 204MHz) advised me to increase waitstate of RWSTATE and see if the problem recurs.

pEEPROM-> = RWSTATE 0x1D0E; (70ns RPHASE2 / RPHASE1 150ns)

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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by laogan666 on Thu Mar 26 06:08:49 MST 2015
I also think so,if you have the answer,please post to me,thank you!
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by capiman on Thu Mar 26 01:48:38 MST 2015
Have you seen errata? I think there is a entry regarding EEPROM and waitstates.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by boscfab on Thu Mar 26 01:09:59 MST 2015
I'm still waiting for a response from italian FAE of NXP.
I have not received explanations about the correct setup of RPHASE1 RPHASE2; the configuration performed by LPCOpen sets with a define "EEPROM_READ_WAIT_STATE_VAL 0x58" and this seems wrong because it does not take into account the  M4_CORE clock.
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by laogan666 on Wed Mar 25 19:26:47 MST 2015

Quote: boscfab
Any news?


I have the question with you.Do you have the answer?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by boscfab on Tue Mar 17 10:17:25 MST 2015
Any news?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by boscfab on Mon Mar 09 02:14:56 MST 2015
I think that in the literature there is more than one error.
Reading the manual UM10503 and LPC435x product data sheet declare that RPHASE1 = 70ns_min and RPHASE2 = 35ns_min.

By analyzing the source code for eeprom_18xx_43xx.ce eeprom_18xx_43xx.h KEIL MCB4357 there are three DEFINE:
#define EEPROM_CLOCK_DIV                 1500000
#define EEPROM_READ_WAIT_STATE_VAL       0x58
#define EEPROM_WAIT_STATE_VAL            0x232

The two values of wait-state for READ and WRITE seem to be wrong!
The value "Tclk" shown on page 1356 of UM10503 rev1.9 refers to the frequency of Core_M4 (204MHz in my case) or the frequency of the EEPROM (1.5MHz) as described on page 1358 of UM10503?
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lpcware
NXP Employee
NXP Employee
Content originally posted in LPCWare by embd02161991 on Fri Mar 06 17:07:05 MST 2015
Hi,

Have you looked at the EEPROM example in LPCOpen software package ?
That could be a starting point.

http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc43xx-packages

Thanks
NXp Technical Support
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