How to get the SDRAM running with 204 MHZ on the LPC4300 Hitex board

[lpcware]

Content originally posted in LPCWare by jokn on Mon Sep 24 07:42:52 MST 2012
I spend a lot of time to get the SDRAM running with 204 MHZ on my LPC4300 Hitex board as well as on my custom board.
Start point was the CMSIS Library Vers. 2012-05-31 the project
\Examples\EMC\Emc_Sdram

I found this thread:
http://www.lpcware.com/content/forum/sdram-controller

And added the following code to set the EMC to operate at 100 MHz withh the CPU at 200 MHz using EMC_CLK_DIV.

LPC_CCU1->CLK_M4_EMCDIV_CFG = 0x21; // enabled / divide by 2 for 100Mhz
LPC_CREG->CREG6 = LPC_CREG->CREG6 | 0x10000; // set EMC_CLK_SEL

But this did not get real success. The maximum CPU speed was still 156 Mhz.
After reading the LPC43xx user manual  a little more detailed. I found another very important parameter the

EMC clock delay register.
At that  moment I set the EMC clock delay to more than 2.0 ns it works fine and all other timing parameter seems getting harmless.
Finally I set the clock delay the maximum of 3.5 ns

LPC_SCU->EMCDELAYCLK = 0x7777 ;  // 3.5 ns EMC clock delay

[lpcware]

Content originally posted in LPCWare by bavarian on Wed Nov 21 09:31:44 MST 2012
Hello Jokn,

if you work with a different toolchain, then the requested files would push you only deeper into the toolchain mud ;-)

It will be easier to study the register settings done in the C file and transfer them to your environment.
In the H file there are just defines  which are easy to overtake.
The following appnote gives you also quite some good hints for SDRAM usage with our chip:

http://www.lpcware.com/content/nxpfile/an10935-using-sdrddr-sdram-memories-lpc32xx

Another note to the Hitex board and SDRAM: I have seen on some boards problems with 204/102MHz configurations. This seems to be related to the SDRAM bus timings. In the attached picture you see a patch which delays the CLK0 clock timing slightly. If you see that your board e.g. works at 192/96MHz but not on 204/102 then add this capacitor as shown in the picture. I used 10pF.
LPC_SCU->EMCDELAYCLK = 0x6666 normally works fine.
If the CLK0 timing is at the limit (depending on the board design), then it would be better to use CLK2 for the SDRAM clock input. It comes slightly different and provides a little bit more margin --> always use CLK2, then you have more margin. And a pad for a small capacitor wouldn't hurt as well, if you do a PCB.

Regards,
NXP Tech Support Team

[lpcware]

Content originally posted in LPCWare by jokn on Wed Nov 07 10:07:39 MST 2012
Hello bavarian,

I spend some time in another project so first today I will try your example program.
Unfortunately we are working in very different environments. Thus my compiler dos not find some include files from your project.
Could you please make me a package with all the include files you ar using in your example?

Project includes
#include "lpc18xx_43xx.h"
#include "system_LPC18xx_43xx.h"
#include "scu_LPC18xx_43xx.h"
#include "config.h"

Thanks
Jokn

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Oct 02 07:54:33 MST 2012
Hello jokn,

it shouldn't be so bad that you need to work with maximum delay ;-)

Check the attached code which works fine for the Hitex A2 and A4 board.
From your application code you just need to call EMC_Init(). Please position this object into internal SRAM in case you have your code located in the external flash at 0x1C000000. You can't execute code from the external memory and at the same time change the configuration of the interface.
This code works fine for me at 192MHz (--> 96MHz for the EMC, check the define CLKOUT_HALF). 204MHz should be possible as well, but I need to check the SDRAM configuration en-detail.

Best regards,
NXP Technical Support.