How to get the SDRAM running with 204 MHZ on the LPC4300 Hitex board

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by jokn on Mon Sep 24 07:42:52 MST 2012
I spend a lot of time to get the SDRAM running with 204 MHZ on my LPC4300 Hitex board as well as on my custom board.
Start point was the CMSIS Library Vers. 2012-05-31 the project

I found this thread:

And added the following code to set the EMC to operate at 100 MHz withh the CPU at 200 MHz using EMC_CLK_DIV.

LPC_CCU1->CLK_M4_EMCDIV_CFG = 0x21; // enabled / divide by 2 for 100Mhz
LPC_CREG->CREG6 = LPC_CREG->CREG6 | 0x10000; // set EMC_CLK_SEL

But this did not get real success. The maximum CPU speed was still 156 Mhz.
After reading the LPC43xx user manual  a little more detailed. I found another very important parameter the

EMC clock delay register.
At that  moment I set the EMC clock delay to more than 2.0 ns it works fine and all other timing parameter seems getting harmless.
Finally I set the clock delay the maximum of 3.5 ns

LPC_SCU->EMCDELAYCLK = 0x7777 ;  // 3.5 ns EMC clock delay