hd design for fast execution

[lpcware]

Content originally posted in LPCWare by petekol on Thu Nov 19 07:15:11 MST 2015
Hi all,
sorry for the dummy q here...

i want to use full power of 204mhz CPU having of ~1Mb binary that needs ~250KB of ram and can't come up with hw design.

My problem is that 104Mhz Quad SPIFI is ~x30 slower then internal SRAM. Code partitioning is not the option.

Fastest that i can imagine is that i copy all the code to external 32bit SRAM that run at 204mzh but still it looks like it is ~x2 slower than internal SRAM or even internal Flash? For external SRAM i need custom board that is also no option for me.
External SDRAM boards exist. Is SDRAM much slower than SDRAM?

what are other options for me to get close to internal SRAM execution that is good enough for my appl?

thnx,
petekol

[lpcware]

Content originally posted in LPCWare by petekol on Tue Dec 01 08:39:29 MST 2015
thank you for the answer

i think exactly about last proposal you made: LPC4357  + external SDRAM. I thought that external SDRAM is faster than internal flash, is not it?

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Nov 24 06:41:00 MST 2015
[list]
  [*]  There is no way to come close to the execution speed of internal SRAM.
  [*]  A qSPI flash on 102MHz already includes internal wait cycles, so I think above 90MHz operation you don't win that much.
  [*]  Performance of execution from SPIFI for "average code" should be between 20%-40% of execution from internal SRAM. When you see it performing x30 slower, then something is wrong in your software. Did you look at the SPIFI clock to verify that it runs on 102MHz?
  [*]  It is perfectly possible to write code which let the flash accelerator perform bad (the one from the SPIFI and also the one for the internal flash). For a Coremark test we achieved quite good results for the SPIFI execution (more in the 40% range), but with other code it can be worse.
  [*]  Execution from 32-bit SDRAM can be in the range of 15%-25%, when you run on 102MHz you can't make use of the highest SDRAM speed of 120MHz. Herew the problem is that inbetween the read bursts there are relatively long breaks.
  [*]  Code optimzation is maybe the key. Could you partition the code in such a way that you have the executable code in SPIFI, const data in SDRAM and your parameters and stack/heap in internal SRAM?
  [*]  Would the LPC4357 with external SDRAM be an option? Code in internal flash and parameters and stack/heap spread on internal SRAM and external SDRAM?
[/list]

Regards,
NXP Support Team