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Dual Core Example in lpc43xx CMSIS Library

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by jokn on Mon Sep 24 07:16:33 MST 2012
I'm testing the LPC43xx CMSIS library Vers 2012-05-31.
Here the dual core example:
/Examples/DUALCORE/Int_Demo.

The SPIFI Version works fine on my custom board as well as on the hitex board.
Then I tried the to run the M4_RAM target configuration and always get a Hard Fault (Vector Table Fault)
I spend al lot of time to find out the reason for such a strange behavior. Finally inspected the debug initialization file:
LPC43xx Internal SRAM.ini
and found some initializations for the M0 core.
When I comment out the Pre_setuo() statement, the Hard Fault vanished an the project works fine including the IPC communication with the M0 core

Does anybody know what is the real intention of the M0 Pres_Setup() and why it causes a Hard Fault?

FUNC void Pre_Setup (void) {

/* configure M0 for infinite loop */
_WDWORD(0x10080000,0x00001F00);/* dummy stack pointer */
_WDWORD(0x10080004,0x000000D5);/* reset handler */
_WDWORD(0x100800D4,0xE7FEE7FE);/* jump to itself instruction for M0a */
_WDWORD(0x40043404,0x10080000);/* M0 shadow pointer. */

/* release M0 from reset to allow Jtag access */
_WDWORD(0x40053104,(~(_RDWORD(0x40053154))) & (~(1<<24)));

}


FUNC void Setup (unsigned int region) {
  region &= 0xFF000000;
  SP = _RDWORD(region);                          // Setup Stack Pointer
  PC = _RDWORD(region + 4);                          // Setup Program Counter
  _WDWORD(0xE000ED08, region);                   // Setup Vector Table Offset Register
}


/* prepare M0 for access, if needed */
//Pre_setup();

/* uncomment the following line if using a Jlink, and uncheck the "load application at startup" */
/* checkbox inthe project settings > debug window in uVision */
/*
LOAD "keil_output\\LPC43xx Internal SRAM\\example.axf" INCREMENTAL
*/

Setup(0x10000000); // Get ready to execute image in SRAM

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