GPIO interrupt registers

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by Divya on Tue Oct 22 22:29:27 MST 2013
In LPC43XX, among GPIO interrupt registers there are three registers.
1.ENAF (Pin interrupt active level (falling edge) interrupt enable register)
2.SETENAF (Pin interrupt active level (falling edge interrupt) set register)
3.CENAF (Pin interrupt active level (falling edge interrupt) clear register)

I am unable to differentiate between the operation of ENAF and SETENAF when both are 1.
And also when ENAF is 0 and CENAF is 1.
And I am also unclear about the exact functionality of the above registers.

If anyone could explain me with an example it would be helpful.
Thanks in advance.