lpcware

LPCOpen returns wrong dividerIndex for LPC_ETHERNET->MAC.MCFG

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by qwaszx on Fri Jun 21 04:53:49 MST 2013

In file enet_17xx_40xx.c function:


<em>uint32_t Chip_ENET_FindMIIDiv(LPC_ENET_T *pENET, uint32_t clockRate)</em>


returns <em>(dividerIndex-1)</em> that it should.


For example for System Clock Rate 120MHz and clockRate 2.5MHz it returns 12. This means that clock divider for MDC is 44, and MDC freq = 120 / 44 =  2.73MHz


To correct this issue following table should be changed:


 STATIC const uint8_t EnetClkDiv[] = {<span style="text-decoration: underline;"><em><strong>4,</strong></em></span> 4, 6, 8, 10, 14, 20, 28, 36, 40, 44, 48, 52, 56, 60, 64};


And does anyone know why every "Maximum AHB clock supported" in table 159 of UM10562 "LPC408x/407x User manual" (page 215) equals <em>(divider*2.5)</em>, but for dividers 36,40,44 it equals <em>(divider*2.5 - 10)</em>?

Outcomes