EMC SRAM Delay after writing address

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by npeterson on Fri Jun 19 10:04:16 MST 2015
We are developing a product that is using the LPC4078 processor using the EMC to communicate to an FPGA that has registers that appear as SRAM to the microcontroller. The CPU is running at 120MHz, we have the EMC set to run at 60MHz, and the FPGA is running at 24MHz.

Most of the time we can interact with the FPGA without an issue, but sometimes when writing a register and then quickly doing another write or read to the FPGA the idle time between the is only about 32ns, which is shorter than the FPGA clock. We have set the "STATICWAITTURN" register have a delay of 175ns (register value of 0xa) but it does not look like the value in this register is getting applied after SRAM writes. However it does appear to be applied after reading from the SRAM.

It appears that all the EMC configuration registers are setup correctly. We have also ensured that the EMCBC bit in the SCS register is set to 1 to disable burst mode as described in section 9.10 of the user manual.

In the attached screen captures CLK is the 24MHz FPGA clock.

Is this the expected behavior of the EMC? I figured that the value set in the "STATICWAITTURN" register would be applied to both reads and writes, but it looks like it is only getting applied to reads.