Watchdog on the LPC4088

[lpcware]

Content originally posted in LPCWare by jdowd on Wed Jun 25 13:55:01 MST 2014
I'm having trouble making the watchdog fire on this processor. The example code I've found is for the LPC11XX family.

I have programmed for a minimal watchdog with no Warn or Protect enabled. Just a straight count down from the default value of 0xff.
This means that I have a 0x03 in the Mode register (enable and Reset). I leave the TC register alone since it's reset value is 0xff. I then "feed" the watchdog once and only once. I then turn on the WDT_IRQn vector and enter a loop.

I have a console programmed up and in it I can look at the TV register value. It is only ever 0xff. No decrement ever happens and the watchdog never goes off.

I have looked at the User Manual and there is a dedicated oscillator to drive the watchdog functionality and it does not appear to have to be "selected" or enabled. There is mention of a PCLK but amount of searching shows a bit in anything that will enable the watchdog.

This is different than the LPC1768 in which the clock has to be selected for the watchdog. So, any demo code I find is only able to be compiled if I use a 1768 and not a 4088.

Here is my starting code snippet....

  NVIC_DisableIRQ(WDT_IRQn);

  /* Setup the Watchdog timer operating mode in WDMOD register */
  theValue = *(uint32_t*)(this->theBaseRegister + Watchdog::WDT_Register_MOD);
  theValue = (theValue & ~(theModeBM)) | theModeBM;
  *(uint32_t*)(this->theBaseRegister + Watchdog::WDT_Register_MOD) = theValue;

  /* Set a value for the Watchdog window time in WDWINDOW if windowed operation required */

  /* Set a value for the Watchdog warning interrupt in the WDWARNINT register if a warning interrupt is required */

  theValue = *(uint32_t*)(this->theBaseRegister + WDT_Register_MOD);
  theValue |= WDT_Mode_Running;
  *(uint32_t*)(this->theBaseRegister + WDT_Register_MOD) = theValue;

  /* Enable the Watchdog by writing 0xAA followed by 0x55 to the WDFEED register */
  __disable_irq();
  *(uint32_t*)(this->theBaseRegister + WDT_Register_FEED) = 0xaa;
  *(uint32_t*)(this->theBaseRegister + WDT_Register_FEED) = 0x55;
  __enable_irq();

  /* The Watchdog must be fed again before the Watchdog counter reaches zero in order
   * to prevent a Watchdog event. If a window value is programmed, the feed must also
   * occur after the Watchdog counter passes that value.
   */

  NVIC_EnableIRQ(WDT_IRQn);


Cheers!!

[lpcware]

Content originally posted in LPCWare by jdowd on Wed Aug 27 11:03:54 MST 2014
Thanks for your reply.

I have looked it over, compiled it and made sure it worked. Unfortunately my application needs to run as a slave and not a master. I'm trying to figure out how much clock information is still required to setup the rx/tx side. I can't quite figure out the requirements reading the User Manual.

And...

Why does the STATE register always show 0x07 as it's value? You can't seem to clear it, if the "level" of the RX FIFO is 0, then how can there be an Rx IRQ pending? I've set the RX Fifo level to 4.

Cheers!!

Oops!!

At the time of this posting I was pursuing the I2S interface as well. I must have been thinking about it when I wrote this reply. Sorry for the confusion.

Cheers!!

[lpcware]

Content originally posted in LPCWare by xianghuiwang on Fri Jun 27 18:00:23 MST 2014
Hi jdowd,

There is a lpc4088 watchdog sample project in our lpcopen package

http://www.lpcware.com/content/nxpfile/lpcopen-software-development-platform-lpc40xx-packages

You can reference the periph_watchdog example within the peripheral workspace.

Regards!