lpcware

Timer0 interrupt.

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by lenguyen on Fri Apr 04 13:27:25 MST 2014
Hi All,

I am working on to make a timer0 interrupt at our rate every 1 msec.
Here's my Code:

void Timer0Init(uint32_t timer_freq)
{

/* Enable Timer 0 clock */
Chip_TIMER_Init(LPC_TIMER0);

/* Timer 0 setp for match and interrupt at TIMER0TICKRATE_HZ */
Chip_TIMER_Reset(LPC_TIMER0);
Chip_TIMER_MatchEnableInt(LPC_TIMER0, 1);
Chip_TIMER_SetMatch(LPC_TIMER0, 1, (timer_freq / TIMER0TICKRATE_HZ));
Chip_TIMER_ResetOnMatchEnable(LPC_TIMER0, 1);
Chip_TIMER_Enable(LPC_TIMER0);

/* Enable timer 0 interrupt */
NVIC_ClearPendingIRQ(TIMER0_IRQn);
NVIC_EnableIRQ(TIMER0_IRQn);

}

void TIMER0_IRQHandler(void)
{
        // Toggle GPIO1
        toggle_io1 = ~toggle_io1
        Chip_GPIO_WritePortBit(LPC_GPIO, 5, 2, toggle_io1);


if (Chip_TIMER_MatchPending(LPC_TIMER0, 1)) {
        Chip_TIMER_ClearMatch(LPC_TIMER0, 1);

                // toggle GPIO2               
                toggle_io2 = ~toggle_io2
Chip_GPIO_WritePortBit(LPC_GPIO, 5, 3, toggle_io2);

}
}

Here's what I see on GPIO.
- GPIO P5.2 toggles every 2.5 uSec
- GPIO P5.3 toggles every 1 msec.

I put the break point in timer 0 ISR routine and the timer 0 MCR = 0x18, that makes sense. My question is why the timer 0 ISR comes every 2.5 usec instead of every 1 msec ?

Thanks
LN



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