lpcware

I2S interface State Register

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by jdowd on Mon Jul 21 11:16:15 MST 2014
On reset the state register of the I2S module are set. The user manual states that the bit reflects the presence of an interrupt for either the Rx/Tx side or there is a bit each for DMA1 or DMA2 interrupts pending.

Can anyone verify that these bits are actually working? I've run the demo s/w for the I2S and those bits never change. There does not appear to be a way of clearing them.

My own code gets interrupts on the Tx portion of the i/f but those bits still never change no matter what actual state the i/f is in.

I really need some clarification on this interface.

I'm running in slave mode as well. I'm not sure how that can affect these "state" bits but there it is.

Cheers!!

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