lpcware

Internal EEPROM wait state register

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 15, 2016 by lpcware
Content originally posted in LPCWare by qwaszx on Mon Jun 30 05:27:45 MST 2014
Can`t understand the calculations.

There is following In documentation (UM10562 chapter 37.5.1.5):

... Programming a zero will result in a one cycle wait state.

PHASE3 = ( 15ns * cclk) - 1 = (15ns * 120MHz) - 1 = 1.8
Therefore, PHASE3 = 2

...
Table 725. EEPROM wait state register (WSTATE - address 0x0020 0090) bit description

7:0 PHASE3 Wait states 3 (minus 1 encoded).
The number of system clock periods required to give a minimum time of 15 ns.


But when i calculate:
(15 * 0.120) - 1 = 1.8 - 1 = 0.8
then round to nearest bigger integer = 1

What have i missed? Should i decrement or not?

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