LPC 4337 - Any constraints on simultaneous AHB transfers

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by jackgeotech on Thu Apr 02 10:48:20 MST 2015
I'd appreciate an authoritative answer to a question about the AHB bus on the LPC4337.

The diagram "AHB multilayer matrix master and slave connections" - Fig. 11 in the UM10503 - implies that there are no constraints or arbitration delays on bus transfers as long as each peripheral group is accessed by only one master at any given time.

For greater clarity, in the LPC4337 (which has no Subsys M0 core) there are 11 masters and 11 slaves.  So in an extreme case, each of the 11 masters could be accessing a different slave, all at the same time, and there should be no conflict or arbitration delays.

I have assumed that this is true, but I have not been able to find an unequivocal statement in the NXP documentation.  For some of the other NXP chips it is clearly stated that there are no arbitration delays as long as two masters don't try to access the same slave.  I have not been able to find a similar statement for the LPC43xx.

Out of curiosity, what is it that is "multilayer" about the "AHB multilayer matrix"?  I don't see multiple layers in Fig.11.  So I'm wondering if the real structure is more complex than shown in Fig. 11, possibly introducing some constraints.