Help on configuring PLL on LPC3131

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by BasicPoke on Tue May 10 08:50:34 MST 2016
On the LPC3131, can I please get some help on how to set up the PLL for a certain frequency.  I am not really understanding the documentation in the user manual UM10314.  Here is the sample code I have.  Do I only need to set the 3 dividers?

  //PLL Init 180MHz
  HP1_MODE = 0x4;     //Power Down PLL

  HP1_FIN_SELECT = 0; //Select FFAST as Pll input clock
  HP1_MDEC = 8191;    //M divider
  HP1_NDEC = 770;     //N divider
  HP1_PDEC = 98;      //P divider

  HP1_SELR = 0;
  HP1_SELI = 16;
  HP1_SELP = 8;

  HP1_MODE = 1;       //Enable PLL

  while(!(HP1_STATUS & 1)); //Wait untill PLL locks

Also, I am seeing 90 MHz on the CLOCK_OUT signal.  Is it normal for this to be the main clock divided by 2?

Thanks for any help.