lpcware

LPC31xx: SPI peripheral issues

Discussion created by lpcware Employee on Jun 15, 2016
Content originally posted in LPCWare by kenh6942 on Thu Aug 22 07:11:57 MST 2013
Issue #1:

This may only be relative to the CDL; I did not check the linux patch. lpc313x_spi.h defines SPI_TXFF_FLUSH as _BIT(1). This should be _BIT(0).

Issue #2:

When the peripheral enters and leaves sequential multi-slave mode (SMS), it appears that the device cannot actually leave that mode and return to normal operating mode without a software reset/re-configuration.

In my case, I have a SPI flash on CS0 and two other devices connected to CS1 and CS2. During typical operation, I enable SMS and the two devices on CS1 and CS2 are selected/enabled and used. However, I need to be able to disable SMS and allow updates of the SPI flash. Given the variable length of messages to SPI flash, using SMS would mean constantly adjusting the word count for the slave for each communication. When disabling SMS, clearing the FIFOs, selecting a single slave, and then re-enabling SPI, the STATUS register shows the SMS_MODE_BUSY bit being set and no SPI bus communication occurs. Disabling SPI does not clear the SMS_MODE_BUSY bit. The only recourse is to, as said above, reset and reconfigure the peripheral and slave configurations.

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