/*D*/ uint32_t dummy_send[2] = {0x12345,0x343424}; /*D*/ uint32_t dummy_receiver[2] = {0}; LPC_SC->PCONP |= (1 << 29); // enable DMA power LPC_SC->DMAREQSEL |= (1<<1); // source Timer0 LPC_GPDMA->IntTCClear = (1<<1); LPC_GPDMA->IntErrClr =(1<<1); //NVIC_EnableIRQ (DMA_IRQn); LPC_GPDMA->Sync |= 0; //syncing DMA channel ( 1- disable) LPC_GPDMA->Config = (1<<0); //b0- enables DMA module/ b1=0 little endian LPC_GPDMACH[GPDMA_CHANNEL1]->CSrcAddr = (uint32_t) &dummy_send[0]; LPC_GPDMACH[GPDMA_CHANNEL1]->CDestAddr = (uint32_t) &dummy_receiver[0];//&LPC_GPIO1->PIN; LPC_GPDMACH[GPDMA_CHANNEL1]->CLLI = 0; LPC_GPDMACH[GPDMA_CHANNEL1]->CControl = (2<< 11) //data size |(1<< 12) //Source burst size |(1 << 15) //Destination burst size |(2 << 18) //Source transfer width |(2 << 21) //Destination transfer width |(0 << 26) //Source increment |(0 << 27) //Destination increment |(1 << 31);//count interrupt is enable LPC_GPDMACH[GPDMA_CHANNEL1]->CConfig = (0<<0) //channel enabled |(0 << 1)//source peripherial |(0 << 6)//dest peripherial |(0<<11)//transfer type |(0<<14)//int error |(0<<15)//terminal count mask |(0<<17) // fifo has data |(0<<18); // disable dma requests LPC_GPDMACH[GPDMA_CHANNEL1]->CConfig |= (1<<0); //enable |