EMC Static Memory Back to Back Access Timing

Discussion created by lpcware Employee on Jun 15, 2016
Latest reply on Jun 18, 2016 by lpcware
Content originally posted in LPCWare by bayside on Mon May 02 08:30:11 MST 2016
We are interfacing an FPGA to the EMC Static Memory Interface on a LPC 3240 and therefore need to understand the timing of that interface.  Page 58 and 59 of the LPC 3240 datasheet (attached) show the timing waveforms of the static memory interface with reference to the appropriate static timing configuration registers.

What is not illustrated in these diagrams is the timing of the signals when back to back memory access are performed.  e.g.  If back to back memory writes are preformed (in non-page mode), how long is the chip select brought back high between subsequent writes?  Is this timing configurable?

I found the configuration register for the "Static Memory Turn Round Delay", but that only applies to back to back access involving a read first.

Since our FPGA will be ran at a slower clock rate than that of EMC Static Memory Interface, we need to add wait states to stretch out the memory timing to ensure the FPGA "sees" all memory interface signal transitions.  It looks like if no configuration for the timing between back to back memory access is possible, our FPGA can miss the CSn pulse which would occur between accesses.  This can be worked around, however we would like to understand all possible configurations first.