Content originally posted in LPCWare by kenh6942 on Wed Jan 02 06:27:18 MST 2013
I've been having issues getting the latest CDL set to run on the ea3141 board and am looking for further information on how to fix it given what I have found so far:
Referring to files included with the v0.06 CDL release:
- The MCU appears to stop in cgu_init_clks() (located in lpc313x_cgu_drivers.c) right after it disables the fractional dividers before setting up the dynamic dividers. Curious that there's a '#if 1' for this section, almost like someone was having issue with it and allowed for disabling the dynamic configuration until they could figure out what was wrong.
- This is only a problem if HPLL1 is set to run at 270MHz. If I set HPLL1 to 180MHz, no problem. I've checked all the divider settings when running at 270MHz and made adjustments to make sure the various parts are running at the same frequencies as when running at 180MHz, but no luck.
- I can run the HPLL1 up to 210MHz before it becomes a problem; anything higher and clocks stop once the fractional dividers are disabled.
I've contacted EA about this and they didn't have any immediate insight. I'd been trying to get onto the lpclinux forum for the past week with no luck and now the site is completely offline.
If anyone has any thoughts on how to resolve this, it would be greatly appreciated.
