SDRAM questions

[lpcware]

Content originally posted in LPCWare by tvink on Fri Dec 19 08:26:17 MST 2014
Hi,

Just read through AN11508, SDRAM Interface, and have a couple of questions.  I am using a single x16 SDRAM ( 4M x 16bit ).  My CPU is the LPC1837JET256.


I am looking at figure 6 in the app note. 

- Can I use any single DYCSx line that I want as long as the coresponding CKEx line is also used?

- For 16 bit I will be using DQM1 and DQM0 only.  Correct?

- What do I do with the feedback pins, CLK0 and CLK2?  Just a pad with no trace routed?

- Inside the CPU the signals are listed as EMC_CLK01 and EMC_CLK_23 but the pins CLK0 and CLK2 are used.  Do I really use pins CLK0 and CLK2 or
  should I be using pins EMC_CLK01 and EMC_CLK_23.  On the 256 ball package EMC_CLK2 and EMC_CLK_23 are on different balls.

- Lastly, is there a approved vendor listing of SDRAMs?

Thanks

[lpcware]

Content originally posted in LPCWare by bavarian on Tue Jun 14 06:11:00 MST 2016
As you are using the same SDRAM as on the LPC1850 Hitex board, please use this simply as reference. Schematic wise as well as software setup wise.

You made one mistake: A13 and A14 are used for BA0 and BA1
The series resistors are good style, but if you have problems to fit them on your PCB you could also leave them out. They would reduce a little bit the overshooting effect (causes radiation) when the SDRAM drives data into direction LPC1830. The edges the SDRAM generates are quite steep. From the LPC1830 you get less steep edges
For the LPC1830 flashless version of the LPC1800 it might not be bad to foresee a footprint for a small capacitor (2.7pF - 12pF) from CLKx to GND.
There is a problem with this on the LPC4300 platform when running on frequencies above 180MHz, so this does not necessarily apply for the LPC1800.
But just in case you're running into trouble you could delay the CLK signal a little bit with this capacitor.

Regards,
NXP Support Team

[lpcware]

Content originally posted in LPCWare by Honey@mani on Sat Jun 11 05:08:45 MST 2016
Hi,

I have a doubt that why we need to use mask pins .

[lpcware]

Content originally posted in LPCWare by tvink on Mon Feb 23 08:18:35 MST 2015
Hi,

I've been away from this for a while and what I think I understood had to be relearned today.
Anyway would you review the attached JPEG to sanity check my SDRAM connection to the LPC1837?

I am using a single 16 bit SDRAM device and am patterning the connection after AN11508, figure 6.  ( Best performance using a single device and CCLK Div2 )

I am booting from internal flash so I do not have any of the boot option resistors connected.

I have the two EMC_DQMOUT data mask lines connected to the SDRAM upper and lower byte mask pins.

I am treating the SDRAM bank selects as address lines.  ( BA0 and BA1 on the SDRAM )
I am assuming that address lines EMC_A12 and EMC_A13 are not ROW / COL muxed and can be used as I have shown.

I chose EMC_DYCS0 as my chip select and am using EMC_CKEOUT0 to go with it.

I am using CLK1 to drive the SDRAM and am leaving CLK0, CLK2 and CLK23 unconnected.  ( Guess I could use CLK23 for another pin function but there isn't an alternate that I need )

Some more neurons are firing but I am not there yet!   So I am updating this posting with some additional questions....
I am trying to figure out how the banking works and how interleaving is programmed.  The app note uses EMC_A14:13 for bank select ( table 1 ) but I think that would leave holes in my memory map.  ( I am using a 64Mb "16 bits x 4 banks" device )  I am also reading the users manual UM10430 chapter 21.  Table 364 and 365 look like they have the answers to my banking questions but I am not sure how to read the tables.  Table 365 has two mappings for my 64Mb device.  One is for Roe, Bank, column and the other is for Bank, Row, Column. To the left there are 4 groupings of addresses.  Dont know how to read this.  Do they map to the three items ROW, COL, Bank?  but how to map 4 things to 3?   And there is no A13 in this mapping.  So I think my answers are here but need some additional help figuring it out.

Thanks




Did I misunderstand anything?

Thanks,
Tony

Edit:  I had the byte masks reversed so I uploaded an updated JPEG

[lpcware]

Content originally posted in LPCWare by bavarian on Wed Jan 07 08:20:32 MST 2015
1) Can I use any single DYCSx line that I want as long as the coresponding CKEx line is also used?

Answer: Any DYCSx can be used


2) For 16 bit I will be using DQM1 and DQM0 only. Correct?

Answer:  Yes


3) What do I do with the feedback pins, CLK0 and CLK2? Just a pad with no trace routed?
Inside the CPU the signals are listed as EMC_CLK01 and EMC_CLK_23 but the pins CLK0 and CLK2 are used. Do I really use pins CLK0 and CLK2 or
should I be using pins EMC_CLK01 and EMC_CLK_23. On the 256 ball package EMC_CLK2 and EMC_CLK_23 are on different balls.

Answer:  You need to select one CLKx pin as clock source for the SDRAM, the other 3 pins need to be unconnected. The option to use combined clocks CLK01 or CLK23 offers you additional clock pins CLK1 and CLK2 to be used for other purposes. In this case you use CLK0 as SDRAM clock and leave CLK2 unconnected.


4) Lastly, is there a approved vendor listing of SDRAMs?

Answer: No, all existing SDRAMs fulfill the same specification, some with more margin than others.


Design hint: please foresee a small capacitor footprint on your PCB which connects the SDRAM clock signal to ground (for example from CLK0 to GND). The reason is that at higher frequencies above 180 MHz a bug in the EMC takes effect (see error sheet and app note "2.2.5 Core clock divide by 2"). Delaying the clock signal slightly with a 10pF capacitor helps to recover from this.

Regards,
NXP Support Team